The aim of the set of posts in this section of this blog category is to develop an USB protocol debugger and analyser that can extract USB 2.0 data, from a USB data stream, in real time and fed the stream to a PC, which will typically host a Linux operating system. Although some processing of the USB data stream may take place in the FPGA in the first instance the stream will be buffered in external memory attached to the FPGA and sent in its raw form to the PC.
The FPGA we will use for this purpose will be Altera's Cyclone V (5CEFA2F23C8N) FPGA found on Arrow's BeMicro CV Development Board. If the 5CEFA2F23C8N cannot cut the mustard, then we should move up to the the BeMicro CV A9, which in comparison contains the 5CEFA9F23C8N, a FPGA that is more than 10 times larger than the FPGA found on the BeMicro CV.
Alternatively, since neither board has an embedded SoC processor, in the future we could use one of the Cyclone V SoC devices or Xilinx's MicroZed Evaluation Kit containing a Zynq-7010 FPGA. For now we will begin the project using the BeMicro CV, which although not feature packed includes the essentials required for this project. These are namely an abundance of external memory and an exemplary number of I/O pins, as well as the fast FPGA, of course. We intend to make the most of these essential features for this project.
The USB 2.0 Protocol Debugger and Analyser Architecture
The USB 2.0 Protocol Debugger and Analyser Architecture can be seen in the block diagram, below. It consists of two USB 2.0 physical layers, which are used as USB endpoints to intercept and capture the USB packets. These packers are received and transmitted between a USB host and a USB slave devices.
A FTDI UM232H-B, USB Hi-Speed (USB 2.0) device is used to transmit the captured packets, between the USB host and USB slave devices, to the Linux PC. The 1GB of DDR3 memory on the BeMicro CV development board should be used as a contiguous FIFO to prevent data overflows. Communication between the UM232H-B device and application software on the Linux PC should be undertaken using FTDI's ftd2xx libraries.
Finally, the BeUSB3.0 development platform, containing the Cypress FX SuperSpeed USB 3.0, should be used to additionally and experimentally stream captured USB packets to a Linux PC. Although our primary goal does not encompass using this device the objective of including it in the design is two-fold. Firstly, it will provide valuable experience in learning about USB 3.0 and Linux device drivers. Secondly, it will allow us to determine the suitability of upgrading the USB 2.0 protocol debugger and analyser to a USB 3.0 one.
The Main Protagonists
The picture below shows the development boards and kits acquired to create the architecture described previously. Each board or kit will be comprehensively examined, as they are actually used and interfaced to the FPGA. Right now we merely introduce them. The BeMicro CV has been looked at briefly previously. It consists of a FPGA with approximately 25,000 Logic Elements (LEs) and 50 embedded 18 x 18 multipliers, which could be useful for filtering streaming data.
Although not consisting of a large FPGA, by any means, the BeMicro CV (1) does bring the respectable number of I/O pins to the party that are needed. While the USB3.0 development platform connects to the BeMicro's 80-pin connector the 2 x20 way headers consisting of 36 general purpose I/O pins each should be used to connect to the USB 2.0 physical layers and the UM232H-B
Items (3), in the Figure above is the BeUSB3.0 described previously, while items (2) are the two USB 2.0 physical layers, the USB3300. These PHYs or Hi-Speed USB Physical layer transceivers can actually act as a slave, host or OTG device. For the purpose of this exercise we shall use it as neither. They will only be used to route packets between the link layers and the FPGA, as raw data. They consist of a low pin count interface (ULPI), which is ideal for our project.
Finally, item (4) is FTDI's USB Hi-Speed USB 2.0 device. It consists of a FIFO that is used to transfer data of a rate up to 480Mb/s and is used to conveniently handle the USB signalling and protocols that would have otherwise been implemented in the Cyclone V FPGA. This is the device that we shall firstly interface to the FPGA in the next part of this blog series.