- Created on Saturday, 05 March 2011 10:24
- Last Updated on Friday, 02 September 2011 15:54
The ProASIC3 (PA3) family of FPGA's from Actel, like most FPGAs, require an external clock source when programmed with synchronously clocked logic. When designing a PCB that hosts the PA3 device a common question that is usually asked is; "To which pin of the PA3 device do I connect an external oscillator?". Well, given the PA3's vast number of I/O pins, that could be suitable for the task, this is a very reasonable and tricky question indeed.
If we examine the named pins of the A3P1000 device, in the PQ208 package for example (see Figure 1), then one is confronted with a mixture of global I/O pins, regular I/O pins and an array of power pins. To the regular developer of FPGA centric hardware connecting external oscillators, that are used to drive synchronous logic, to the global I/O pins would be the familiar choice.
Connecting an external oscillator to a global pin allows, the external clock source, direct contact with the global clock distribution network. The global clock distribution network is internal to the PA3 device and connecting to it is a fundamental requirement. It ensures that all of the clocked logic, within the FPGA, is driven synchronously with the minimum of clock skew.
Figure 1 : The ProASIC3 A3P1000 FPGA in the PQ208 package consists of four I/O banks. The PLL device is located in Bank 3 of the A3P1000 device.
However, given the nature of the PA3 device, the external oscillator could be used in conjunction with the internal Phase Lock Loop (PLL), too. Hence, understanding the fabric's clocking architecture could help influence ones decision, as to which one of the vast number of global I/O pins an external oscillator could be connected to.
The first place to look for information, when designing for any FPGA, is the FPGA's data manual. However, at over 660 pages in depth, the ProASIC3 FPGA's one can be particularly daunting. This can be especially so for the new or unfamiliar developer, attempting to layout a Printed Circuit Board (PCB) that hosts a PA3 device, for the first time.
This brief tutorial therefore explains how one could connect an external oscillator to the A3P1000 device, although it is equally applicable to the FUSION and SmartFUSION family of devices, also manufactured by ACTEL corp (www.actel.com). The design criteria for this brief tutorial therefore, is to connect an external clock source to the A3P1000 FPGA, in the PQ208 package. The clocking source should also be routed through the PLL internal to the PA3 device.
To begin with then lets try and locate the PLL infrastructure within the FPGA. The Actel PA3 family of FPGAs consists of, what are termed, Clock Conditioning Circuits (CCCs). The CCCs serve the same general, although not identical, purpose as the Digital Clock Managers (DCMs) in Xilinx devices. The PLLs in Altera's devices and the sysCLOCK blocks in Lattice Semiconductor devices serve the same purpose. It should be noted however that the PLLs within Actel's FPGAs, like some of the other vendors, are pure analog ones.
Figure 2 : The CCC with integrated PLL can be found on the middle of the west side of the A3P1000 device in the PQ208 package. The CCCs without PLLs contain programmable delaly functionality. [Image Taken from the ProASIC3 nano FPGA Fabric, User’s Guide, Actel Corp,. 2010]
The CCCs comprise of two variants, one with an integrated PLL and the other without. As the name suggests the CCCs are used to synthesise an incoming clock signal. That is, it allows the user to add a programmable or fixed delay, phase shift and/or apply frequency division, to the clock source. The CCC also allows for clock synthesis, by frequency multiplication, to internally and externally connected input clock signals.
The PA3 device, in the PQ208 package, is categorised as having four I/O banks. The CCCs are associated with the I/O banks and are located at the four corners of the device. They are also located at the middle of the east and west sides of the device. Out of the 6 CCC locations described above the one that we are interested in for this particular tutorial, that is the CCC with integrated PLL, is located in region F at the centre west side of the device. Its position is highlighted in red in Figure 2 above.
Each Clock Conditioning Circuit (CCC) has 3 clock inputs and each clock input can be chosen from a set of 3 multiplexed global I/O pins. This can be seen in Figure 3 below. To locate the multiplexed global I/O pins, associated with a CCC, it is important to understand how Actel's pin naming convention corresponds to the pin's function and location.
Figure 3 : Corresponding to each pin are the 3 clock inputs associated with a clock conditioning circuit. The inputs into the CCC are the three clock inputs CLKA, CLKB and CLKC. Each clock input has 3 multiplexed sub-inputs A0, A1 and A2 for CLK A and similarly named sub-inputs for clocks B and C.
Global Pin Naming Convention
Each global I/O pin is signified by having a G prefix, preceded by a section letter. For example, to locate the global pins associated with the CCC with integrated PLL, in section F, it is necessary to locate the pins labelled GFxy. It should be noted however that not all sections on a particular device contain CCCs with integrated PLLs. Generally, the more dense pin packages, especially the Ball Grid Arrays (BGA), have a larger and more complete array of global pin locations, CCCs and associated PLLs, compared to the smaller packaged Quad Flat Pack (QFP) devices.
Figure 4 : The global pin naming convention of Actel devices.
The last letters in the global pin name, xy, indicate the connection to the multiplexed clock inputs. The x indicates to which of the three CCC source clock inputs the pin is associated with and the letter y indicates one of the three multiplexer inputs. for that particular source. For example, pins GFA0 (pin 26), GFA1 (pin 28) and GFA2 (pin 30) are all global I/O pins associated with the clock input source A, CLKA of the CCC in section F, in the A3P1000 device of the PQ208 package.
Clock Conditioning Circuit Electrical Timing Characteristics
To appreciate the input timing limitations of an oscillator, used as an external clock source to the PA3, it is necessary to understand the PA3's Clock Conditioning Circuits electrical timing characteristics shown in Figure 5 below.
Figure 5 : The ProAsic FPGA's Clock Conditioning Circuits Electrical Timing Characteristics. [Repeated from the ProASIC 3 Handbook, pp160, Actel Corp., 2009]
Some of the most important properties for the design engineer to note from the table, shown in Figure 5, is the Clock Conditioning Circuits (CCCs) input frequency, in_ccc and its output frequency, out_cc. This tells us that the minimum input frequency that can be applied to the CCC, in_cccmin is 1.5MHz and the maximum frequency, in_cccmaxis 350MHz.
Likewise, the minimum frequency that the CCC can be expected to synthesise, or condition, an externally input clock source to, out_cccmin, is 0.75MHz and the maximum output frequency, out_cccmaxis 350MHz. We could conclude therefore that the maximum frequency that we should expect our synchronous logic to operate at is 350MHz.
PLL Power Supply
Associated also with each CCC's integrated PLL is the requirement for a power supply. The recommended operating power supply voltage is between 1.4V and 1.6V. However, since the power supply used to power the the core logic of the PA3 is typically 1.5V, it is not uncommon to power the analog power supply of the PLL also at 1.5V. Using the same 1.5V power supply even, with an appropriate power supply decoupling scheme, is not uncommon.
Figure 6 : The analog power supply's recommended operating voltage is between 1.4V and 1.6V.
The PLL has a separate power supply for a number of reasons including:
- For the energy conscious application it allows the PLLs circuitry the luxury of being powered down when not in use, thus saving energy.
- Having a separate analog power supply, in a mixed signal design environment, allows the designer to isolate the analog supply from the fast switching noise generated by the digital circuit. If the noise generated by the digital circuit couples onto the analog circuitry, the PLL circuitry for example, the anlog circuit could ultimately produce erroneous results.
As mentioned previously, although the PLL power supply can be made available from a separate power supply, it can also equally originate from the same supply used to power the internal digital logic when an appropriate power supply decoupling scheme, like the one shown Figure 7 below, is used.
Figure 7 : Shows the typical setup when an external oscillator is used to drive the synchronous logic in the PA3 device. The external oscillator (1). The chosen input pin (2) allows connection to the Clock Conditioning Circuit. The CCC (3), with integrated PLL, allows synthesis of the clock input source. A separate power supply input (4) for the PLL allows for analog power supply isolation from unwanted digital I/O switching noise.
CCC and PLL Software Configuration
The CCC can be configured using CCC-dynamic, Clock-delayed or PLL-static configuration wizards. For example, imagine that it is required to use an external 40MHz oscillator to not only drive the synchronous logic in an FPGA, but also to synthesise 133MHz and 9MHz clock sources. The clock synthesised sources could be used to drive an external SDR SDRAM IC and an LQ043T3DX02 display respectively, as can be seen in Figure 8.
Figure 8 : An external oscillator connected to the A3P1000 FPGA can be used to drive an external SDR SDRAM as well as the LQ043T3DX02 display when configured using the CCC PLL static configuration wizard (1). The PLL Static core (v2.1) (2) can be used to initiate the PLL wizard as well as the CCC Dynamic (v1.1) core.
To configure the PLL, integrated within the CCC, it is necessary to use the SmartGen static PLL (or CCC-dynamic) configuration wizard that is part of the Libero IDE (v9.0) software. Libero is freely downloadable, in certain configurations, from Actel (www.actel.com) and is available for both the Microsoft Windows and LINUX operating systems although at the time of the writing of this article, the free licensing options are only available with the Microsoft Windows version.
An example use of the configuration wizard can be seen in Figure 9. In this figure we are informed that when the external oscillator is set as the input source, with a frequency of 40MHz (1), and output frequencies of 133MHz (4), and 9MHz (5), are requested. Here, the PLL provides us with usable synthesised frequencies of 132.941MHz and 8.863MHz respectively, as well as the original 40MHz (3).
Figure 9 :The PLL configuration wizard is used to synthesise 132.941MHz and 8.863MHz when 133.000MHz and 9.000MHz clock frequencies are requested respectively. The HDL files that can be included in ones project can be generated by clicking on the "Generate" button (6).
Also, a clock lock signal, item (7) in the diagram, provides the designer with a trigger to verify that the PLL has correctly locked onto the clock input frequency and is providing synthesised copies on its output.
The CCCs with integrated PLL available to ProASIC3 FPGA devices and the related mixed signal equivalents, the FUSION and SmartFUSION FPGAs, are accessible through the global clock pins of the device. By correctly locating the global pin associated with each CCC, it is possible to provide a rich triplet of synthesisable clocks that can be used to accurately drive the FPGAs synchronous internal logic. The synthesisable clock could be used to drive externally clocked devices too.
Figure 10 : The entity when using the clock configuration named "testpllcore" in this case, can be seen in this figure. The signals shown on the interface are available along with some others depending on the configuration options selected. The CLKA signal is connected to an external clock source through a global I/O pin using a clock buffer. The POWERDOWN signal, as its name suggests, is used to switch the PLL circuitry off when not in use. The LOCK signal is used to determine when the PLL has successfully synthesised the incoming external clock signal. The generated clock signals used to synchronously drive user logic are the interface signals GLA, GLB and GLC.
The omission of global differential clock inputs pins is glaring and inconvenient, yet the combination of the global clock distribution networks and the clock conditioning circuity provides a very powerful solution for synchronising internally gated logic. It allows FPGA designers wishing to implement multiple cross-clock domains the luxury to do so. The clock-rich FPGA fabric of the PA3 family is further enhanced in the ProASIC E family of FPGAs which have up to 6 PLLs further enhancing multi-clock domain designs in particular and all designs in general.