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Creating a DE0 Nano Quartus II Project



Quartus II is Altera's premier software for everything, not unsurprisingly,  to do with compiling, synthesising and programming designs targeted at their FPGAs. Its Altera's "Swiss army knife" for their brand of FPGAs and SOC products. This note provides a method, that could be used, to setup a Quartus project for the DE0 Nano development and education board. The web edition of Quartus version II, with service pack I installed, was used to make this application note. 

 Creating the Project


To realise our objective, it is necessary to start the Quartus II software and navigate to the "New" dialog window by clicking on "New" in the "File" menu item. The "New" dialog window that results presents the opportunity to create a "New Quartus II Project" ....


....  and leads to  the new project wizard seen above.


The first page allows you to provide a working directory, name and top-level design entity for your project.


The following page allows you to add design files. If you do not add any design files here you can always do so later on. I didn't add any files here.


On the third page things become a bit more interesting, as this is where you enter the details of the FPGA on the DE0 Nano board. The FPGA is the Cyclone IV E, EP4CE22F17C7, in the FPGA 256 package. Well it was more interesting than the previous dialogs.


This page allows linking the project to different EDA tools. I didn't have any things to add here so I left it blank and moved on to the next page.


A summary of all your hard work is presented on the final page. 


There is an opportunity to add files by clicking on the "Files" tab and right clicking on the file icon that appears as a result. 


 As well as adding files, the "Files" dialog can be used to remove unwanted design files too.


If all has gone well, then it could be time to assign pins to the top-level design by locating the "Pin Planner" in the "Assignments" menu. Values can be entered either by typing them in or by selecting    from a list of drop down entries.


At this stage you should be able to click the "Compile Design" item in the Flow menu and be rewarded by critical warnings due to a constraints file not being found. This can be remedied by locating the TimeQuest Timing Analyser  in the "Tools" menu.


The TimeQuest Timing Analyser allows for the creation of a Synopsis Design Constraints (SDC) File. The user is provided with a text editor used to create a clock, set clock groups, set input output delays and all that good stuff associated with constraint files.


In my case all went as expected and the "Programmer" dialog was used to program the FPGA on the DE0 Nano board with a .sof file using JTAG.


  1. Chapter 7. The Quartus II TimeQuest Timing Analyzer, The Quartus Handbook, Altera Corp., Nov 2011.
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