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Series 1: Part 1 - The Mechanical and Electrical Interfaces (LQ043T3DX02)


The objective of Series 1 of the Missing Lecture Notes (MLN) series is to develop A LQ043T3DX02 (Sony PSP) Display Driver Board. In this part of the series the importance of considering the mechanical interface is introduced. The electrical interface is also considered and the appropriate voltage levels, to drive the display, are presented. The reader is also introduced to the data interface in this first part of the series. In the final section of this article the sequencing of the digital and analog voltage rails is investigated.


The SHARP LQ043T3DX02 is a digital LCD-TFT module used as the replacement display in Sony's PSP hand-held games console (datasheet link - coming soon). This screen is ideal for use in Field Programmable Gate Array (FPGA) hosted projects, because FPGAs have digital I/O's in abundance and the display is primarily driven by a digital interface.

Due to its digital interface, interfacing to this TFT-LCD module is relatively straight forward, as there are no analog RGB signals to digitise into their digital equivalent. Instead, the digital to analog conversion circuitry resides within the TFT-LCD module itself. The purpose of the series of articles presented here is to investigate how to create a generic, general purpose digital interface to drive the TFT-LCD module using a FPGA. The aim, also, is to explain how to display meaningful data using an embedded GUI written in VHDL (Hopefully!) or at least how to write VHDL modules to drive the display.


An annotated representation of the Sony PSP replacement display is shown in Figure 1 below. The screen has an image resolution of 480 horizontal pixels by 272 vertical pixels and has an active display area of 95.04 mm x 53.856 mm (I am not sure why one display area dimension is given to 3 decimal places and the other is given to 2 decimal places in the datasheet? In my time, at university, you would have had 2% - 5% of the examination mark deducted, in the mechanical design course, for doing something like that!).

Figure 1: An annotation of the Sony PSP display and its dimensions.

A summary of the mechanical specifications are given in the table below.

Item     Value
Screen Size     109 mm
Active Area     95.04mm x 53.86mm
Pixel Format     480 x 272 Pixels
Unit Outline Dimensions     105.5mm x 67.2mm x 3.95mm
Mass     50g
Backlight System     7 x LED

The screen's interface consists of two flexi cables, one of which supplies the power to drive the backlight unit. This unit includes the seven backlight LEDs which provide the brightness to the screen. The other flexi cable carries the analog and digital power signals for driving the TFT panel and its driver ICs. Also included on the second flexi cable are the digital timing signals and the 24-bit RGB data signals used to display images on the screen.

Preliminary Investigation

In order to ease the design of a daughter board, that will be used to drive the TFT-LCD module, the specifications of a driver module have been broken down into three separate sections. I have called these sections interfaces and I have listed them below with a short explanation of what each one represents. From now on each interface will be treated separately, in a modular fashion, and during the final design considerations they will be brought together.

The Mechanical Interface : This interface will deal with all the physical aspects of the design including which connectors to use, where to place the connectors in relation to each other and the flexi cables. Also, it will be used to consider how to house the TFT-LCD module in an enclosure. All these tasks might sound trivial and mundane but they still need to be done!

The Electrical Interface : This section will provide all the information needed to ensure that the appropriate electrical specifications are met. It will focus on obtaining the appropriate voltages for the power supply rails, the voltage ramp rates of the power supplies as well as the digital voltage levels of the I/O signals.

The Data Interface : This interface will look at the timing and data signals of the TFT-LCD module and it will be used to investigate how to display images on the screen. Questions that will be answered, when considering this interface, include how much memory does one need to create a video system that has front and back video buffers? The amount of memory required to create a scrolling image map like the type used in console games will also be considered.

Getting the mechanical and electrical interfaces right is extremely important as any mistakes made can not be corrected programmatically unlike the data interface. Instead any errors made in the mechanical or electrical interface designs will result in a costly PCB re-spin, which will consume both time and money. In the case of the electrical interface an error can be so extremely severe that the LCD-TFT module can be completely damaged too. Any electrical equipment interfaced to the display may also be destroyed. Generally an electronics's hobbyist has plenty of time but not much money so getting the design right the first time round can not only be extremely rewarding psychologically but will save some cash too.

Given the critical nature of the interfaces described above the suggestion is that as much time and effort as possible is expended on the mechanical interface in conjunction with the electrical interface. Once these two have been completed the rest of the time will be spent on implementing the data interface. However, as I am familiar with the data interface from previous projects, I am not complete ignoring one aspect of the design in favour of the others. I am "merely" postponing its implementation.

The Mechanical Interface

The backlight (1) and data input (2) flexi cables, required to interface the TFT-LCD module to external circuitry, are shown in the Figure 2 below. The backlight unit connector should be a 0.5mm 4-pin FPC connector. A Kyocera part is recommended in the LQ043T3DX02 datasheet.  However, after making some inquires about the part, I decided that it  is relatively impossible to get hold of, in small order quantities at least. I have replaced it with an almost equivalent Hirose part. The FH19C-4S-0.5SH is similar in terms of the pitch size, however it does not offer the same strain relief as the Kyocera part.  It will just have to do.

Figure 2:The two connectors required to interface to the display are the 4-way FH19C-4S-0.5SH and the 40-way FH12-40S-0.5SH.

The power, data input and timing interface, labelled (2) form the panel driving interface and connect to external circuitry through a 1mm pitch Hirose connector, the FH12-40S-0.5SH(55). This interface is used to power the TFT-LCD module's driver ICs as well as display imagery on the screen. By using the TFTLCD module's outline dimension in the datasheet the centre-to-centre distance of the connectors should be a maximum of 14.71mm (During the PCB layout stage this dimension turned out to be wrong - B.P).

This is all that needs to be done for the mechanical interface for now, next we will look at the electrical interface.

The Electrical Interface

In this section we will look at the electrical specifications of the TFT-LCD panel driving circuitry. We will start by looking at the absolute maximum voltage ratings, which are listed, in the Table 1, below. As can be seen in the table the TFT-LCD module requires a 2.5V digital power supply and a 5V analog power supply. What this table tells us is that the 2.5V supply must never exceed 4.5V and must not be less than 0V. Likewise, the 5.0V analog supply must not be greater than 6.0V and must not fall below 0V.

Table 1: The Absolute Maximum Ratings of the LQ043T3DX02. [Taken from the LQ043T3Dx02 datasheet, Sharp Corp., 2005]
If the electrical characteristics of the panel driving circuitry, listed in Table 2 below, are now considered,  the different operating voltage ranges can be seen. The table shows the minimum, typical and maximum operating values of the power supply voltages (the power supply voltage and current values have been encircled and labelled (1), in the table, for clarity).

The design engineer is expected to design a circuit that works at the typical operating voltages, which are 2.5V and 5.0V for the digital and analog power supplies respectively. However, he is secure in the knowledge that even if he cannot match these power supply values exactly the circuit will still operate, as long as the power supply voltages remain within the recommended minimum and maximum operating ranges shown in the table.

Table 2: The electrical characteristics of the LQ043T3DXo2 display.  [Taken from the LQ043T3Dx02 datasheet, Sharp Corp., 2005]

Also quoted in the first part of this table are the typical and maximum dc current ratings, that each power supply can consume. As almost all electronics systems have a power budget, it is important for the design engineer to know the maximum power consumption of the the TFT-LCD module. This will be factored into the overall power budget of the system. Hence, what is of extreme interest in the table above is the maximum amount of DC current that the digital and analog supplies will consume.

If PMAX = Maximum Power, Maximum Current = IMAX and the Maximum Voltage = VMAX then the maximum amount of power consumed by each power supply is given by:


The calculated values for the maximum power that can be consumed by the 2.5V supply and the 5.0V supply under normal operating conditions are given in the table below.

Maximum Voltage     Maximum Current     Maximum Power
2.5V     3mA     7.5mW
5.0V     18mA     90mW

Note that these values are different from the absolute maximum rating values. Operating the circuitry outside of the minimum and maximum operation values will result in the TFT-LCD module not working correctly while operating it outside of the absolute values is likely to damage the TFT-LCD module irreparably.

The next section we will look at, in the TFT-LCD panel electrical characteristic's table, contains the low and high input voltages (encircled (3) in the table above). To do so we must first define what these values actually mean. The VIL is the maximum voltage that can be applied to an input data or timing signal for it to be considered to be at a logic level of '0'. In this case it is 0.2 x VCC or 0.5V, when the digital power supply voltage,VCC, is considered to be 2.5V. Hence, any device that will be used to drive the TFT-LCD panel's data or timing signals must be capable of providing an output low voltage, VOL, of 0.5V or lower.

Likewise, the VIH is the minimum voltage that an input data or timing signal can be at for it to be considered to be at a logic level of '1'. According to the value given, in Table 2, this is 0.8 x VCC or 2V again when VCC is considered to be 2.5V. Again, this means that for an external device, like an FPGA, to drive the TFT-LCD panel's data (or timing signals) to a logic level '1' the device must be capable of providing an output high voltage, VOH, of at least 2.0V. The VIH and VIL of the TFT-LCD module are shown graphically in the diagram in Figure 3, below.

Figure 3: Logic voltage levels required to drive the LQ043T3DX02 display.

So what do these values actuslly mean in the real world? Well, suppose that we want to drive the TFT-LCD module with a FPGA from the PA3 device family from Actel. Then it would be considered reasonable to investigate setting the I/O bank, that contains the I/O pins that will drive the TFT-LCD module, to 2.5V LVCMOS as the digital power supply of the TFT-LCD module is 2.5V.

Table 3: Actel's PA3 family of devices 3.3V LVTTL and 3.3V LVCMOS input and output logic voltage levels.  [Taken from the PA3 datasheet, Actel Corp.]

However, as can be seen from the diagram, in Table 3 above, doing this will be an absolute disaster as the VOL and VOH voltages of the 2.5V LVCMOS settings fall within the noise margin of the TFT-LCD device and will not set the TFT-LCD module data and timing signals to the logic levels expected. The correct thing to do is set the I/O bank to 3.3V LVTTL.

Sequences of Supply Voltages and Signals

The final issue to handle, in this part of the initial installment of the series, is the order in which to apply power to the analog and digital voltage rails as well as the display's digital signals. This sequence is shown graphical in Figure 4 below.

LQ043T3DX02 sequences of supply voltages and signalsFigure 4: LQ043T3DX02 sequence of supply voltages. [Adapted from the diagram in the LQ043T3Dx02 datasheet, Sharp Corp., 2005]

This diagram shows the start-up sequence labelled  in yellow and the shutdown sequence labelled in blue and is pretty much self-explanatory. For example, the digital power supply voltage, Vcc must be powered-up at most 10ms (time period t1_c) before the analog power supply voltage, AVDD. The sequencing of supply voltages and signals can be found the LQ043T3DX02's datasheet and is further investigated in a future part of the series.


This introductory article, in the series on developing a driver board for the Sony PSP display, has provided a methodical approach to designing a daughter board. The design has segmented the design into mechanical, electrical and data interfaces, each of which shall  be considered in future articles in the series. The article has also laid the ground work for the type of logic levels expected from driver ICs. The second installment of the series will concentrate on the data interface.


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