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Series 1: Part 2 - The Data Interface (LQ043T3DX02)

Abstract

The objective of Series 1 of the Missing Lecture Notes (MLN) series is to develop A LQ043T3DX02 (Sony PSP) Display Driver Board. In this part of the series attention is focused on the data interface of the design. The timing characteristics of the clocking, video synchronisation and RGB data signals are considered. Also, the memory requirements of a video frame store are discussed. Finally, the digital and analog power supply voltages and sequencing are re-visited.

2.1 Introduction

In the previous article, part 1, an investigation has been started into using the TFT-LCD module, the Sharp LQ043T3DX02 used as the display screen in the Sony PSP hand console, as a display in hobby and homebrew projects. The previous article specifically looked at the mechanical and electrical interfaces of the module. In this article I will look at the data interface of the TFT-LCD module and how signals are sent across the interface, to the display, to create an image.

2.2 The Data Interface

The signals that make up the data interface are provided in Section 4 of the module's datasheet and are repeated in a condensed form in Table 1 below. Details of how 24-bit RGB and 32-bit RGBA computer generated images are displayed can be found in many excellent computer graphics text books (Foley and Van Dam, Hearn, Apple etc). I will not repeat that information here, instead I will look at how we can drive the screen given the timing characteristics in the datasheet and the data signals listed in Table 1.




Table 1: TFT-LCD Module Data Interface Signals

2.3 The Timing Characteristics

The timing characteristics of the TFT-LCD module provide all the information necessary to successfully display an image on the screen. This information can be found in Section 7 of the datasheet and repeated below in Figure 1. I have further divided this timing characteristic table into sections for explanatory purposes only.



Figure 1 : TFT-LCD Module Timing Characteristics. [Taken from the LQ043T3DX02 datasheet from SHARP Crop.]


2.3.1 The Clock

According to the data, in section (1) of the timing characteristics table, the TFT-LCD module should be driven by a clock signal that has a typical frequency of 9.00MHz, although any value between 7.83MHz and 9.26MHz will suffice. It is very expensive if not impossible to manufacture a crystal oscillator that will output a frequency of exactly 9.00MHz. This is due to manufacturing tolerances, operational temperature variations as well as other parameter variations over time. Hence the TFT-LCD module provides quite a bit of leeway regarding the clock frequency that can be used.

This is a great advantage as the source driving the screen (e.g a FPGA demo board) might not have a 9MHz oscillator available. Instead the 9MHz clock frequency may have been derived from a frequency that is not a direct multiple of 9. If, for example, a FPGA prototype board only has a clock input frequency of 80MHz, how would one derive the clock signal required to drive the TFT-LCD module? Would the dervied clock frequency be within the TFT-LCD modules specifications? What if the FPGA does not have any internal PLLs?

Some of the specifications (Fox FX-HC736R-27) of a 27MHz oscillator can be seen in the first part of Figure 2. It has a frequency stability parameter (1) with a specified value of +-25 PPM (Parts per Million). This tells us that the oscillator has an output frequency of anywhere between 27MHz - 25Hz and 27MHz + 25Hz but not 27MHz exactly.

Some manufactures also display an aging value, parameter (2) in Figure 2, for example +-5Hz.This value must also be taken into account when considering the variation in an oscillator's output frequency. It is really only in time critical applications however that all parameters that can affect the variation of frequency must be accurately accounted for. For the purposes of driving the TFT-LCD module we should use a device that produces a frequency of 9MHz. We should not need to worry about any tolerances or variations as long the frequency generated is within the provided timing specifications.



Figure 2 : Example Oscillator Clock Specification. [Taken from the  FX-HC736R-27 datasheet, FOX]

The clock signal is used to register the RGB data and synchronisation signals into the TFT-LCD module on its falling edge. For the purposes of this article we will derive any frequency related calculations using a clock that has a theoretical frequency of 9.00 MHz exactly. This immediately tells us that the clock period is 111.11ns and that if the image that we are displaying, on screen, is read out from a memory chip then, the memory chip should have a data access time of less than 111.11 ns.

Given the fast access times of modern Static RAM (SRAM) and Synchronous Data RAM (SDRAM) devices the memory requirements, in terms of access times at least, are not that stringent and standard off-the-shelf memory chips should suffice when used as a video frame store.

The timing characteristics of the clock also specify that it should have a duty cycle of between 40% and 60% but should typically be 50%. A clock that has a duty cycle of 50% is considered to be at a logic level of "1" one-half of the time and at a logic level of "0" the other half of the time. Likewise, a clock that has a duty cycle of 30% is considered to be at a logic level of "1" 30% of the time and at a logic level of "0"  the remaining 70% of the time. This is demonstrated in Figure 3.


Figure 3 : Clock with Different Duty Cycles.


How can a clock which has a duty cycle that is outside the minimum and maximum duty cycle specifications, given in the datasheet, corrupt the R, G, B or video synchronisation signals? To understand how, we need to investigate the next set of parameters in Figure 1, the data setup and hold times.



2.3.2 Data Setup Time (Tds) and Hold Time (Tdh)

The data setup time, Tds, is the minimum time that the data signal has to be stable at a valid logic level before the occurance of the sampling event. Where in this case the sampling event occurs on the falling edge of the clock. If this minimum time period is violated the input data signal's value may not be correctly recognised.


Figure 4 : Data Setup and Data Hold Times. (NB The PSP TFT-LCD Module's clock, CK, registers data on it's falling edge - B.P)

The data hold time, Tdh, is the minimum time the data signal has to remain unchanged after the occurance of the sampling event. Again, a violation of this minimum time period may render the input signal's value invalid. If we look at Figure 4 it seems that all three clocks should successfully register data into the LCD-TFT module on the falling edge.

So how can data corruption occur if we use a clock which has a duty cycle that is outside the minimum and maximum duty cycle specifications given in the datasheet? Well, supposing internally, in the TFT-LCD module, both edges of the sampling clock are used to register the incoming R, G, B or synchronisation signals as can be seen in Figure 5. For arguments sake supposing that the D-type flip-flops have a propagation delay of 5 ns.


Figure 5 : Example Showing How Both Edges of a Clock are Used to Register Data. (NB: The PSP TFT-LCD Module's clock, CK, registers data on it's falling edge- B.P)


We now begin to see how we can run into trouble if the duty cycle of our clock is outside of the given specifications. If the duty cycle of the clock is out of the bounds of the specifications then, in this particular example (see Figure 5), data corruption can occur when the data registered by the rising edge of the clock by device A is not fully stable before it arrives at the second device B that uses the falling edge of the clock.

Finally, as an aside, if we were to use a 9 MHz oscillator with the frequency specifications given, in Figure 2 above, would the VOL and VOH voltages level be suitable? In the next section we will look at the synchronisation signals and how they are used to "frame" an image on the screen.


2.3.3 Horizontal and Vertical Synchronisation

The timing characteristics data shown in Figure 1 can be visualised as a screen layout like in Figure 6 below. The area we are really interested in is the active video area in the centre, the 480 x 272 pixels squared area where all of our graphics should be displayed. To derive this window in hardware we need to understand the synchronisation parameters in sections (3) and (4) of Figure 1.

Figure 6 : Horizontal and Vertical Synchronisation Timing Data.


The synchronisation parameters provide the timing information used to draw pixels from left to right in the active area by using the horizontal synchronisation data. Likewise, pixels are drawn from top to bottom using the vertical synchronisation data. Now, we can see why the screen is described as having a resolution of 480 pixels by 272 pixels even though the window area is actually 525 x 286 pixels sqaured.

The front porch and back porch timing signals relate to older CRT monitors and are not really relevant to TFT-LCD displays. The terms are still used however for legacy (maintainability) reasons as there are many older computer graphics drivers that encode data using the back porch and front porch timing information. The best way of visualising the back and front porch timing data is to see it as a blanking area that borders or surrounds the active visual area as can be seen in Figure 7. In this blanking period the pixels are normally set to black.


Figure 7 : Front and Back Porch Areas Viewed as a Blanking Area.


2.3.4 Painting a Picture

A typical system used to display a frame of graphics, on the TFT-LCD module, can be seen in the Figure 8 below. A video timing module is used to generate the VSYNC and HSYNC signals and is also used to generate the timing signals used by the video memory controller. It is the responsibility of the video memory controller to retrieve each pixel of the image from the video store.It is this information that will be displayed in the active video area. The video memory controller must retrieve each pixel within at least 111.11ns, that is, within 1 clock period.



Figure 8 : A Typical Computer Graphics Hardware Architecture.

Typical modern display architectures used in computer graphics systems implement the double buffer architecture consisting of two digital canvases or video frames stores. As one canvas is being displayed as the active window the other one can be updated in the background unobtrusively.

When the update is complete the two canvases are swapped around so that the viewer now sees the new canvas displayed in the foreground while the former one can be updated out of view. When this process of update and display is done very quickly and the images drawn are slightly displaced, the viewer gets the impression that the active window on display consists of moving images.

So how much memory is required to store an image in a single frame store? Well, the screen's active area is 480 pixels by 272 pixels. Assume each pixel will occupy 24-bits of memory. Therefore, the total amount of memory required will be (480 x 272 x 24)/8 Bytes or (480 x 272 x 24) / (8 x 1024) KBytes = 382.5KB.

Now, supposing we have an image that is larger than our active display area say, for example, the background image in a scrolling game which could be 600 pixels by 272 pixels as seen in Figure 9 below. Then we will need more memory than just the amount of memory required to display the active video window.


Figure 9 : Example shows the memory area of a game with a scrolling background compared to the memory area used to display a graphic in the active window. [Screenshot from the game Blood money, Psygnosis]


The amount of memory need for a single frame store in this case is (600 x 272 x 24)/8 Bytes or (600 x 272 x 24)/(8 x 1024) KBytes = 478.125KB. Thus it is important when considering the video memory requirements of the display area in some applications to not only think of the visible viewing area, but also any hidden background imagery that can be scrolled into view.

2.4 The Electrical Interface (Contd. From Part 1)

Part II concludes with the section on Sequences of Supply Voltages and Signals continued from Part 1.


2.4.1 Sequences of Supply Voltages and Signals

In Part 1, we looked at the supply voltages required to power the TFT-LCD screen and in this section we will look at the power supply sequencing requirements, replicated in Figure 10 below, along with some important points highlighted on page 9 of the module's datasheet.



Figure 10 : Modified diagram showing the sequences of supply voltages and signals of the TFT-LCD module. [Taken from the LQ043T3DX02 datasheet. SHARP Corp.]

In the context of the datasheet VCC is used to supply the digital components of the TFT-LCD module and AVDD is used to power the analog components of the module. It is not uncommon for digital and analog power supplies to be separated from each other due to their different noise immunity requirements.

Digital circuits change or switch states at extremely high frequencies, charging and discharging capacitors to ground as they do so. This generates a lot of noise on the ground plane of a circuit. However, because digital circuits are required to be in one of two discrete states, either high or low, separated by a healthy noise margin any noise introduced into the circuitry does not adversely affect the state that the circuit is in.

This is not the case however for analog circuits which can have one of a continuous range of values. Any noise or ripple on an analog power rail can easily distort the output of an analog circuit and this is why a separate analog power rail is sometimes used in mixed-signal electronics.

To isolate the analog and digital power supply rails in mixed-signal electronics popular techniques used include: Using a PCB mounted voltage regulator that rejects ripple, on the supply input, to a high degree. This requires using a voltage regulator that has a good measure of power supply ripple rejection. The degree of ripple rejection is usually found in datasheets as the ripple rejection parameter (Figure 11) and in general linear regulators will provide better isolation compared to switching regulators.



Figure 11: Electrical characteristics showing the ripple rejection data in different formats - [Taken from the LM3540 datasheet.]

If the circuit does not provide the luxury of having separate digital and analog power supply regulators then filtering the digital and analog power rails can be done by using passive component filtering as can be seen in Figure 12 below. Why would it be a bad idea to place the two ferrite beads (in figure 12) in parallel on a PCB?



Figure 12 : Example shows how to use passive component to filter a digital/analog power supply. - Taken from the analog Devices ADV7125 datasheet.


2.4.1.1 AVDD and VCC Rise Times

Quite interestingly the analog supply voltage, AVDD, is required to rise from 0.3V to 4.8V in a minimum of 0.5 ms and a maximum of 50 ms (See Figure 10 ¡V parameter t1_D). To better understand this requirement we need the help of elementary electronics and the equation i = C dv/dt where i is the instantaneous current, C is the capacitance and dv/dt is the rate of change of voltage. We will revisit this equation during the component analysis stage in Part III.

On the other hand the only condition for the successful application of VCC is that it is at 90% of its typical value within 50ms (Parameter t1_C in Figure 10).


2.4.1.2 Power Supply Sequencing

If we look carefully at the notes that accompany the sequences of supply voltages in Figure 10 then AVDD should not be supplied before VCC. To achieve this some form of power supply sequencing is needed to delay AVDD so that it is supplied after VCC. There are many different ways of performing power supply sequencing including using passive components as well as dedicated off-the-shelf ICs. We shall investigate this point further during the component analysis phase of the project.


2.5 Conclusion

In this article we have investigated the data interface of the TFT-LCD module and looked at an example oscillator's timing specifications.  This has been done in conjunction with an examination of the horizontal and vertical synchronisation timing parameters. In the next article, part III, we will start by consider any other components that may be needed as a prelude to performing a budgetary costing analysis. This will enable us to conclude part III by writing a design specification for a prototype TFT-LCD module interface board.

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