- Created on Thursday, 13 October 2011 07:05
- Last Updated on Friday, 20 April 2012 07:00
The objective of Series 1 of the Missing Lecture Notes (MLN) series is to develop A LQ043T3DX02 (Sony PSP) Display Driver Board. In this part of the series a technique used, to develop requirement and design specifications, is demonstrated. Also, it is shown how the design specifications can be used, in conjunction with component's datasheets, to aid the process of component selection and analysis. Finally, some example devices are selected and the budgetary costing of the prototype board is presented.
In the previous two articles, parts I and II, an investigation was begun into using a TFT-LCD module as a display in hobby and homebrew projects. The TFT module, the Sharp LQ043T3DX02, is used as the display screen in the Sony PSP hand-held console. The first article specifically looked at the mechanical and electrical interfaces of the module while in the second article the characteristics of the data interface revealed the requirements necessary to display an image.
In this article we will begin by selecting and analysing suitable components. Our choice of components will be based upon our understanding of the requirements and characteristics from the previous two parts.
3.2 Requirements Specification
The discussion in parts I and II should lead us to a functional diagram like the one shown in Figure 3-1 below. Based upon this diagram we should now be in a position to identify the components required, add any additional components that we think might be useful and finally derive a design specification.
Figure 3-1 : The Functional layout of the project's requirements.
Before we move on to the component analysis and selection stage of the design however, the first thing we should do is to use our functional diagram to derive a list of objectives. This list of objectives is known as the project's Requirements Specification.
It is a good idea in any electronic projects for the design engineer to develop a list of requirements for the project. This provides the framework of objectives that are used to define the design goals of the project. It also helps to determine the end goals that should be achieved before the project can be deemed a success. A preliminary requirements specification for this project is derived from the functional diagram above and is shown in Table 3-1.
Table 3-1: Preliminary Requirements Specification
So these are the requirements that must be met before we can declare our prototype driver board, used to interface to the PSP TFT-LCD display, a success.
3.3 Component Analysis and Selection
Based on the requirements specification, in Table 3-1, we can now begin to analyse and chose components that we think will "fit the bill". Component choice can be heavily influenced by devices that the design engineer has successfully used in previous designs.
However, technology does not standstill and it is important for the design engineer to always consider newer variants of component devices used previously. This will allow the design engineer to take advantage of any new design features or characteristics, the newer devices may have, as they become available.
Power consumption by devices, for example, is always being improved upon in successive generations of the same device or in completely new devices. Thus, it is always important to scrutinise a device's datasheet to see if it meets the design requirements of a new project even if a variation of the same device has been used before.
The subsections below provide a summary of the devices considered for this project and the techniques that have been used to decide whether they are suitable. At the same time I have defined some design specifications based on the characteristics of the selected devices.
3.3.1 [RS01] - 5.0V Power Supply Regulator
Our first requirement is to supply our prototype board with a 5.0V power supply. As easy as this sounds it forces us to make a major design decision immediately! This is because our prototype board may be interfacing to a driver board that already has a 5.0V supply voltage, as will be the case if interfacing to the Xilinx Spartan 3A starter kit.
On the other hand a 5.0V power supply regulator could prove useful if a driver board cannot supply a 5.0V supply directly but instead only has a higher voltage, say 12.0V as is the case with the Cyclone III starter kit from Altera.
For our prototype board however, we will assume that the FPGA driver board supplies the 5.0V directly and therefore we will not need the 5.0V power supply regulator. If in the future we decide to interface to a board that cannot supply 5.0V well, we will have to start all over again!
Figure 3-2: If we assume that our FPGA driver board supplies 5.0V to its connector interface then our prototype board will not need a 5.0v regulator. For this reason the 5.0v regulator is removed from the design.
Hence, as a consequence the specification requirement [RS01] should be closed\cancelled, as shown below.
3.3.2 [RS02] - 2.5V Power Supply Regulator
A 2.5V power supply regulator is required to supply the digital power to the LCD-TFT module. To satisfy the electrical characteristics of the module the regulator should be able to supply, at least, the module's maximum current of 3mA [DS01].
The regulator I intend to use is one from the NCP1117 range from OnSemi (www.onsemi.com). The only reason why I have chosen this device is because I have used it before, quite successfully, on other projects. There are many alternatives that would equally do the job.
Using this voltage regulator is a massive overkill since the current consumption of the TFT-LCD module's 2.5V rail is in the milliamps and our voltage regulator can supply about 1A [DS02]; however, as this regulator is readily available from on-line electronic catalogue companies it is a reasonable choice. The cheap price helps too! It could also be used to power other devices on our prototype board should they require a 2.5V supply.
From this observation and the one above we can derive our first two design specifications [DS01],[DS02] (See Table 3-3 below):
18.104.22.168 The NCP1117-1.0A Low-Dropout Positive Fixed Voltage Regulator
The NCP1117 series of regulators are quite handy Low Dropout (LDO) linear regulators that only require two external capacitors, Cin and Cout to regulate an incoming voltage as can be seen in Figure 3-3 below.
The input bypass capacitor, Cin, is required for stability if the voltage regulator is located more than a few inches from the power source. In our case this is most likely as the power source will be on the FPGA driver board. Likewise, the output capacitor, Cout, is required for output stability.
However, unlike the input capacitor which is optional the output capacitor is mandatory. As we cannot anticipate the distance of the power source (which will be on the driver board) to our prototype board in advance we shall use both capacitors.
Figure 3-3: NCP1117 Voltage Regulator Schematic Diagram Overview.
Our prototype board is likely to be used on a desktop with adequate ventilation and hence we need not be concerned, at this stage of the design at least, in the temperature variations of the electrical characteristics or about the device's junction temperature.
We will re-visit these aspects of the design when we consider a more technically demanding variation of the prototype board in the future. An electrical characteristic parameter of interest however is the dropout voltage labelled (2) in Figure 3-4.
Figure 3-4: A snippet of the NCP1117's electrical characteristics taken from the NCP1117/NCV1117 datasheet. the input voltage to the device must be greater than the output voltage (1) and the dropout voltage (2). [Taken from the NCP117 datasheet, On Semiconductor, Nov 2010]
The dropout voltage is the amount of voltage consumed or "dropped" by the operation of the voltage regulator. A consequence of the dropout voltage across the regulator is that the minimum input voltage required for the regulator to operate is Vout + Vdropout.
Consider the dropout voltage characteristic in Figure 3-4 and assume that we will consume 500mA of current. Then, the minimum input voltage, Vin, that can be applied to our prototype board for the regulator to function correctly is 2.5V + 1.01V or 3.51V [DS03].
3.3.3 [RS03 ]- Passive Filter Circuitry
I am not sure whether we really need to worry about the ripple voltage emanating from the digital power supply. It could prove a useful exercise to undertake however especially if in the future we ever connect the TFT-LCD module to a FPGA driver board that emanates a lot of electrical noise.
So here we go! In Part II, of the series, we anticipated the need for some type of electronic filtering circuit to protect our analog circuitry from noise emanating from the continuous, fast switching digital circuitry and other sources. This usually occurs in the form of voltages from signal traces and IC's coupling onto the analog power supply rails.
Figure 3-5: Low-pass pi-topology filter provides power supply stability and filtering. The TFT-LCD module does not seem to have a separate analog ground plane so we will not create one unnecessarily. However, we will still utilise the power filtering circuitry but without the ferrite bead that provides the ground plane filtering.
A typical filter, required to decouple an analog and digital power rails can be seen in Figure 3-5 above. It is a ladder network electronic filter known as a pi-topology low pass filter and its analysis [DS04] is presented below.
Imagine that the digital power supply consists of a DC component and an AC component and that the AC component in turn consists of sub-components AC1, AC2 and AC3 (Figure 3-6). Then, in general, the capacitors, C1 and C2, offer a low reactance to the AC sub-components and infinite reactance to the DC component.
Hence the capacitors, C1 and C2, provide a pathway for some of the AC voltages to ground, depending on their frequency, but block the DC voltage. The AC voltage sub-components that are not fully conducted to ground by capacitor C1, like AC1 and AC2 in this example are presented to the ferrite bead, which has an inductance L1. The DC voltage is also presented to the ferrite bead.
Figure 3-6: Pi-topology Filter Analysis.
The ferrite bead's inductance attempts to block AC voltages by presenting a high reactance while at the same time the DC component is relatively unaffected. This is because the DC component is presented with an almost zero reactance. Hence the inductor, L1 blocks most AC components like AC2 (Figure 3-6) but not the DC component and some minute AC component, phi.
Any remaining AC voltage should be conducted to ground by the capacitor C2. However, due to the impurities of inductors and capacitors, in general, the power supply voltage, Vo, that appears to the analog circuitry will actually still contain small amounts of AC. The pi-filter however presents a better solution than when filtering with its individual parts.
So what criteria are used to select the ferrite bead? Well, to be honest I am not really sure! I typed "Ferrite Bead Inductor" into an online electronic component company's website and I was presented with just fewer than 1000 entries. A selection filter on the site allows the user to filter down the selection using the following categories: (a) Inductor tolerance, (b) series, (c) resistance, (d) Q factor, (e) Material core, (f) Inductor Type, (g) Inductance, (h) Resonant Frequency.
Presented with all this material, in the end I decided to choose a ferrite bead randomly based purely on its datasheet description of it having the general properties of being ¡§¡K effective for low impedance circuits such as power supply and ground ..." The frequency characteristics of the inductor are shown in Figure 3-7.
Figure 3-7: Frequency characteristics of a ferrite bead.
There is still quite a lot more analysis that needs to be done here to fully characterise the pi-filter and how it works. Howerver, we will need to save this work for a later date or we will never get to design our prototype interface board!
3.3.4 [RS04] – Power Supply Sequencing Circuitry
This section looks at the components and circuitry that guarantee that the analog power supply, AVDD, turns on after the digital supply VCC.
22.214.171.124 ADM6820 - FET Drive Simple Sequencer
The purpose of the power supply sequencer is to ensure that AVDD does not power-up before VCC [RS04]. There are many ways of doing this including using a dedicated IC. Such an IC, dedicated for such a purpose, is the ADM6820 from Analog Devices. Using this device might be considered to be an overkill for this particular application. However, it does the job rather well and provides experience in using a power supply sequencer in mixed voltage designs.
Figure 3-8: ADM6820 Power supply Sequencer Schematic Diagram Overview
The resistors, R1 and R2, implement a voltage divider circuit to the internal comparator which compares the voltage, (Vdd x R2) / (R1 + R2) at (1) to a threshold voltage, Vth = 0.618V (see parameter (2) in Figure 3-8). When the voltage at point (1) is greater than the internal threshold voltage and a voltage is detected at Vcc2 then the gate voltage, at point (3), is turned on.
This gate voltage VGATE is large enough to drive the external n-channel MOSFET. If we take a look at Figure 15, in the ADM6820's datasheet, it can be seen that the time delay associated with the gate voltage varies slightly with temperature. However, we shall not concern ourselves with this temperature variation in this project.
The values of resistor R1 and R2 have been chosen as 10K. What would be the effect of changing the resistor values of R1 and R2 to 100K each or even 1K each?
Figure 3-9: Electrical Specifications of the ADM6820. [Taken from the ADM6820 datasheet. Analog Devices]
The capacitor, C2, in the diagram allows us to set a sequencing delay on the voltage AVDD based on the formula:
tDelay(s) = 2.652 x 10e6 x C2
Thus, when C2 has a value of 100nF then,
tDelay(s) = 2.652 x 10e6 x 100 x 10e-9 or 265.2ms [DS05]
So why have I chosen a delay of 265.2ms? Well, the TFT-LCD module datasheet (Sharp LQ043T3DX02) does not really say how soon after a voltage is detected on VCC that a voltage should be applied to AVDD.
Now, since 100nF capacitors are used frequently as bypass (decoupling) capacitors I thought that this would be a good value to start with. This has been done as it means that all we need to do is order more of the same part rather than a single item of a new part. If the delay proves to be too long or too short we will have to change it. Hence the inclusion of test points!
Figure 3-10: The gate voltage, Vgate, is generated by a charge pump within the ADM6820 which guarantees that the gate voltage is 5.5V greater than the input voltages, Vcc1 and Vcc2. [Specification taken from the ADM6820 datasheet, Analog Devices]
The only reservation I have about using this device is that I am not sure whether it will be available from online electronic catalogue companies in small order quantities. If it is not readily available then Maxim-IC produce an alternative part, the MAX6820, which is not only pin compatible with this part but is available for order directly on their website. We will just have to wait and see how the situation develops.
126.96.36.199 : NIF9N05CL- N-Channel Protected Power MOSFET
As mentioned previously a N-channel MOSFET is required in tandem with the sequencer to switch the analog voltage, AVDD, on at the right time. So how do you go about choosing a N-channel MOSFET? Well, with great difficulty!
The problem really is where do you begin to start? If you visit the website of any popular online electronic component distributor and enter "N-channel MOSFET" into their search engine you end up with over a thousand entries for each site (1,373 - Farnell, 6,923 - Mouser and 1,182 - RS).
Figure 3-11: Maximum rating Electrical Characteristics of the NIF9N05CL. [Taken from the NIF9N05CL datasheet, On Semiconductor, May 2006].
So why did I choose the NIF9N05CL? Well, components from OnSemi have served me well in the past so I decided to visit the OnSemi website to see what N-channel MOSFET they have available. The part needed should be capable of controlling a drain-to-source voltage of a least 5.0V (AVDD). It should also allow a drain-to-source current of a few milliamps, the analog current required by the TFT-LCD module. All these requirements have been meet by using this device as can be seen in Figure 3-11.
The other parameters of importance to this project are shown in Figure 3-12 below. The gate threshold voltage Vgs(th) is the minimum amount of voltage applied to the gate before current begins to flow from drain to source. As the gate voltage increases past Vgs(th) the current flow increases. The power dissipated by the device is given by IdxIdxRds where Id in our case is the current consumed by the TFT-LCD module.
Figure 3-12: NIF9N05CL N-channel MOSFET Electrical Characterisitcs. [Taken from the NIF9N05CL datasheet, On Semiconductor, May 2006].
There are other characteristics of N-Channel MOSFETs that are important but not relevant to this project including the dynamic characteristics. The interested reader is encouraged to learn how to use the dynamic characteristic parameters as well as understand how charge pumps are designed.
3.3.5 [RS05] - Power and Data Connector (FH12-40S-0.5SH)
The data and power connector is a standard 40-pin Flat Flexible Cable (FFC/FPC) type connector popularly used in video display products. It is particularly suitable for high frequency R, G, B signals, that is if you consider 9MHz to be a high frequency signal compared to the connector's intended use of signals with frequencies up to the GHz frequency range!
Figure 3-13: The FH12A-40S-0.55SH connector.
The pinout for this connector is shown diagrammatically in Figure 3-14. It is worth noting the two more design specifications listed below. Also, note that there is no analog ground plane going into the connector [DS06], [DS07].
Figure 3-14: Diagrammatic overview of the pinout of the FH12A Data and Power connector.
3.3.6 [RS06] - Backlight Connector (FH19C-4S-0.5SH)
The backlight connector is used to supply the backlight unit within the TFT-LCD Module. As mentioned previously, in Part I, I found it extremely difficult to get hold of the recommended part in the datasheet and instead decided to use FH19C-4S-0.5SH from Hirose. (Figure 3-15).
Figure 3-15: The FH19C-4S-0.5SH backlight unit connector.
The good thing about this part is that it is available off-the-shelf from online electronic component companies. However, the first thing that hits you when you see it is its small (tiny?) size. At about 2.5mm by 4mm this is going to be an extremely challenging part to solder by hand!
Figure 3-16: Overview of the pinout of the FH19C backlight connector.
The only information provided in the datasheet about the backlight unit is that it consists of seven LED¡¦s. A table of current and voltage ratings are also given (see Figure 3-17). To keep things as simple as possible we will only supply a potential difference of 5V to the backlight unit and not design any brightness control circuitry (Figure 3-16). [This turned out to be completely wrong and a backlight circuit has been derived in part IV - B.P]
Figure 3-17: Electrical characteristics of the backlight connector. [Taken from the LQ043T3DX02 datasheet, Sony Corp,.]
Once I get hold of a faulty unit I will take it apart to have a look inside to see what the backlight unit actually consists of. Meanwhile the electrical characteristics provide us with another design specification [DS08].
3.3.7 [RS07] - High Frequency Signals
Up to now we have dealt with devices that have an accompanying datasheet which tells us how to use the device and how to optimally lay it out on a Printed Circuit Board (PCB). To route our high frequency R, G, B and synchronisation signal traces we also need some guidelines. These guidelines are presented to us as a topic known as Signal Integrity.
To pretend to treat the whole topic of signal integrity here would be as fool hardy as it is impossible. This is because signal integrity is a truly immense subject. So for this design we will only focus on a few points that will help us in creating a stable two layer PCB. I will highlight the necessary and interesting points here and delve into the subject to a greater degree, if required, in the PCB design part of the series.
Figure 3-18: Harmonics Associated with Edge Rates. A 9MHz oscillator with 5ns rise and fall times produces harmful harmonics at frequencies of 26.72MHz, 45.16MHz and 63.3MHz. These higher frequencies must be protected against by the PCB design engineer. [Plots done using LTspice IV available free from Linear Technology's website].
Contrary to popular belief unwanted frequencies or high-energy signals on PCBs are not necessarily caused by high-frequency signals but are due to switching signals with fast edge rates, that is signals that have fast rise (and fall) times. An example of this can be seen in the Fast Fourier Transform (FFT) plot of a 9MHz oscillator with rise and fall times of 5ns shown in Figure 3-18.
The frequency spectrum of digital signals in general contains harmful harmonics up to an equivalent frequency of the rise time given by frise = 1/ (pi x trise) or in the case of the 9MHz oscillator above, 68MHz. This means that the design engineer using a 9MHz oscillator should expect signals with unwanted harmonic frequencies of 26.72MHz, 45.16MHz and 63.3MHz. At these frequencies the signals are high-energy ones which can cause undesirable side-effects (Figure 3-19).
Without paying due attention to signal integrity when designing our PCB undesirable side-effects like overshoot, undershoot and ringing can occur on our signals. These effects can be caused by cross-talk between signal traces, ground bounce from multiple simultaneously switching outputs and from signals reflections when signals are badly terminated to name a few.
Figure 3-19: This diagram shows the effect of high-energy, unwanted harmonics on a signal trace in conjunction with a bad PCB layout. In this example the signal levels of the output of a Xilinx Spartan 3A FPGA are different from what is expected by the TFT-LCD module due to a questionable layout.
To protect our design against these problems we will relay the content of our display signals, between the FPGA driver board and the TFT-LCD module, using microstrip transmissions lines.
188.8.131.52 Microstrip Transmission Lines
The two basic forms of transmission line design for PCBs are microstrip and stripline. To minimize the overall cost of our prototype design it will consist of a two layer PCB with microstrip transmission lines used for laying out the high-frequency video signals.
By using this technique our PCB shall have a ground plane to provide a uniform, low inductance, return current path for our high-frequency display signals. Hence any undesirable or unwanted artefacts shall be reduced to a minimum. This technique will be elaborated upon more during the PCB design phase of the series.
3.3.8 [RS08] - FX2 Driver Board Interface
There are many different commercially available FPGA boards as well as the many DIY boards, containing FPGAs, that are made at home. One popular board that is on the market today is the Spartan 3A starter kit available from Xilinx and it is for this kit that we will design our first prototype interface board.
184.108.40.206 Interfacing to the Spartan 3A Starter Kit
One of the gleaming characteristics of the Spartan 3A starter kit, apart from the 700K user-gates, is the 43 I/O pins made available on a Hirose FX2 extension header. To mate to this header we will require the FX2 receptacle shown in Figure 3-20.
Figure 3-20: 100-pin FX2 receptacle required to mate our prototype board with the Spartan 3A starter kit from Xilinx.
Having 43 I/O pins available on a header might seem to be quite a generous amount as interfacing to the TFT-LCD module itself will not require more than 30 I/O pins. However, if we decide to add other devices later on to the design (see below), either to aid or to improve the design¡¦s functionality, then this number of I/O pins can begin to look like too few very quickly.
To interface to the Spartan 3A starter kit means that we need to understand the electrical characteristics of the Spartan 3A I/O pins. To do this a plot of the VOL , VOH of the Spartan 3A (LVCMOS33) and the VIH and VIL of the TFT-LCD module can be seen in Figure 3-21. What this diagram tells us is that there should be no electrical compatibility problems between the FPGA I/O pins and the TFT-LCD module when the FPGA's I/O pins are configured to use LVCMOS33 signal levels.
Figure 3-21: Diagram shows the compatibility of the Spartan 3A FPGA and the TFT-LCD module when the I/O pins of the Spartan 3A are configured at LVCMOS033 voltage levels.
Having the LVCMOS33 electrical characteristics being compatible with the TFT-LCD module on the Spartan 3A starter kit is a bonus as other devices connected to the same banks of the Spartan 3A FPGA are set to this signalling level too. In fact this is the default setting for the FX2 connector interface in the User Constraints File (UCF) provided with the examples that come with the starter kit.
Figure 3-22: The proposed interface of our prototype board when connected to the Xilinx's Spartan 3A Starter kit.
What are the limits to the amount of current that can be drawn from the Spartan 3A starter kit by our TFT-LCD module interface board? Well, to know this we will have to calculate the amount of current consumed by each device on our prototype board.
Figure 3-23: The FX2 connector's electrical specification. [Taken from the FX2 datasheet, Hirose Corp,.]
An associated question, to the one asked above, is triggered by the product specification table (Figure 3-23 above) which provides a guideline to the absolute limits to which the FX2 connector can be used. A parameter of real interest here is the current rating (1) which tells us the maximum amount of current that can be drawn on each pin on the connector.
This connector has a rating of 0.5A so if our interface board requires a larger amount of current than this, say 1A, then we would need to use two pins to connect power to the prototype board [DS09],[DS10].
3.3.9 [RS09] - Rise Time Control
During our preliminary study of the data interface in Part II of the series it was recognised that the analog voltage, AVDD, must be supplied to the TFT-LCD module in a controlled manner. This was to be done in such a way that the change in the rise time of the analog voltage, AVDD, must not be less than 0.5ms and not greater than 10ms as the voltage changes from 0.3V to 4.8V [DS11].
Our solution was to result to basic electronics and use the equation i = C dv/dt. Using this equation with standard off-the-shelf capacitor values produces the plot shown in Figure 3-25 [DS11].
Figure 3-25: AVDD Rise Control. The plot shows the results of using different off-the-shelf capacitors to achieve the rise control criteria of the analog voltage, AVDD.
3.4 Additional Requirements
The FX2 expansion connector on the Xilinx Spartan 3A starter kit has an abundance of I/Os of which we only require about 75%. Rather than leave the I/O pins that will not be used unconnected we can put them to good use by adding extra functionality that we might find useful as shown diagrammatically in Figure 3-26.
Figure 3-26: The oscillator (10), ROM (11), pull-down resistor (12), test points (13) and bulk capacitor (14) are additional devices that could prove helpful in our design.
3.4.1  - Oscillator
We have already investigated using an oscillator in Part 2 and concluded that a driver board might not have a suitable frequency generator to drive the TFT-LCD module and therefore it would be a good idea to add an oscillator to our board.
Figure 3-27: A SPI serial flash is used as a ROM. It can be used to store fonts, game sprites and images which can be especially useful for constructing start-up screens etc.
The Spartan 3A starter kit is supplied with a 50MHz oscillator. It also, not only has an auxiliary socket that hosts a 133MHz oscillator by default but a SMA socket for a user supplied oscillator. We could have used one of these sockets for our driver board oscillator however, as we might want to interface our design in the future with a driver board that does not have either of these features, we might as well place the oscillator directly on our prototype board.
Also, instead of using a 9MHz oscillator we will add one that has a frequency that is an integer multiple of 9MHz, in this case 27MHz, and down convert the frequency internally within the FPGA to 9MHz. (Before sending it to the TFT-LCD module).
Figure 3-28: Electrically compatibility of the 27MHz oscillator and the Spartan 3A when the Spartan 3A is configured to LVCMOS33 signal levels.
Is our chosen oscillator electrically compatible with the Spartan 3A FPGA on our driver board when the FPGA¡¦s I/O pins are configured to operate at LVCMOS33 signal levels? A plot (Figure 3-28) of the output and input voltage electrical characteristics shows that the devices are compatible with each other.
There is a lot more that we can discuss here including rise time, output enable, jitter, load frequency but that could mean going on forever! We will have to re-visit another topic yet again when we consider a more demanding design in the future.
3.4.2  - ROM
Another additional extra for a prototype board is a ROM device (Figure 3-29). This device can be used as a storage area for fonts, background images and game sprites or to store images for a start-up screen, for example.
By placing the ROM on our prototype board we are removing any dependency of storing data on the FPGA driver board which might not have the capacity to do so anyway. So although the Spartan 3A starter kit has two serial storage devices and a parallel one, it is still a good idea to have an independent storage device of our own on the prototype board.
Figure 3-29: A SPI flash is used as a ROM. It can be used to store fonts, game sprites and images which can be especially useful for constructing start-up screens etc
Also, the device I have chosen is a serial device with a SPI interface. This has been done deliberately so that we can interface a ROM device to the starter kit using the FX2 header without requiring a high I/O pin count as would have been the case if we had used a FLASH device with a parallel bus interface.
Using a serial ROM device also allows us to increase the capacity of the device in the future without being concerned about the pinout. This really helps as we do not really know how much storage capacity we actually need. The electrical compatibility of the SST25V 1Mbit serial flash device and the Spartan 3A is shown in Figure 3-30.
Figure 3-30: Plots show the compatibility between the input and output voltages of the Spartan 3A and the SST25V flash device.
3.4.3 - Display On/Off Pull-Down Resistor
The resistor, R1, in Figure 3-31 below, is a pull-down resistor designed to keep the active-high display ON/OFF signal low and hence the display powered off until explicitly powered on from the FPGA.
Figure 3-31: Pull-down resistor on the DISP signal.
This has been done to allow the FPGA programmer to perform any "house-keeping" duties, if necessary, before turning the display on. The 10K value of the resistor has been chosen arbitrarily and only leads to a minimal power consumption of V2/R or (3.3)2 x 10K or 1.01 mW.
What would be the effect on our resistor, R1, if there is another pull-down resistor, R2, internally in the TFT-LCD Module?
3.4.4  - Test Points
Apart from the normal PCB test points used to test low frequency analog signals it would be nice to have the ability to test some of the higher frequency signals generated from within the FPGA like the synchronisation signals, as can be seen in Figure 3-32.
Either SMA or BNC connectors can be used for this purpose. While SMA connectors are smaller than BNC connectors they are more expensive. I have opted to use BNC connectors although the combined length of three connectors will significantly add to the overall length of our prototype PCB compared to the length of all the other devices combined
BNC connectors come in two termination types 50 ohms and 75 ohms. Older test and measurement equipment will generally be the 50 ohm type of BNC connector with the characteristic white dielectric at its centre. Although this is the type I will be using, 75 ohm cables and equipment will still work it but with some degradation in the signal quality due to signal reflections.
Figure 3-32: BNC connectors can be used as test-points to measuring equipment for measuring the high-frequency signals emanating from the FPGA.
3.4.5  - Bulk Capacitance
This should really be a requirement not an additional extra as having a bulk capacitor is quite an important component to have on a Printed Circuit Board (PCB). However, as most design engineers only provide one as an afterthought it might be a good idea to include the bulk capacitor sub-section here.
A bulk capacitor is used to ¡§smooth-out¡¨ low frequency variations in the incoming power supply to the prototype board. This helps shield the component ICs, on the prototype board, from variations in the power supply irrespective of their distance from it.
A bulk capacitor can be seen as performing the same task as a local decoupling capacitor but on a global or PCB wide scale. While a decoupling capacitor provides a charge bank to protect against local high-frequency variations in the power supply to a particular component or IC, a bulk capacitor provides a large reservoir to protect against low-frequency power supply variations to all of the components on the PCB.
So how much bulk capacitance is needed? Well, supposing we wish to protect the TFT-LCD module against power supply variations, then the bulk capacitance, C is given by C = (Itransient x ttransient)/Vmaxripple.
Figure 3-33: electrical characteristics of the TFT-LCD module showing the permissbile input ripple voltages of the digital and analog supplies. [Taken from the Sharp LQ043T3DX02 datasheet]
So for example, if we expect current transients as large as 1A to last for no more than 5us and if the maximum allowable ripple of the supply voltages to the TFT-LCD module is 100mVp-p as can be seen in Figure 3-33 above, then a bulk capacitor with a capacitance, C = 1 x5x10-6/100 x 10-3= 50uF will be needed.
If this calculation is done for each device on the prototype board we should be able to determine the minimum amount of bulk capacitance needed for the whole board.
Taking into consideration the ESR and ESL values of a capacitor what type of capacitor should be used as the bulk capacitor?
Care must be taken when a capacitor with a large capacitance is used on a PCB as it could mean that special precautions should be taken to work with high and dangerous voltages
3.5 Budgetary Requirements
Right, now that we have analysed and selected the components that we think are suitable for the job, we need to find out how much it is all going to cost. The tabulated cost of the selected components can be seen, in Table 3-2, below. Note that I have randomly chosen some online electronic component companies to price these parts.
However, so as to not take away from the exercise of component analysis and selection I have deliberately omitted the actual suppliers as the reader is encouraged to experiment and select their own parts based on what they think is appropriate.
Table 3-2: Component Cost: An approximation of the cost of the components that could be used on the LQ043T3DX02 driver board.
To fully safeguard our design we could also list some alternative devices as well as alternative suppliers. However, as this is only a prototype we will not bother ourselves with level of detail. A pie-chart showing the relative cost of the 2-layer PCB, all of the connectors and the electronic devices including passives is shown in Figure 3-34.
Figure 3-34: The relative cost of a double-sided PCB and all of the connectors compared to the electronic devices and passives (IC's).
What is the relevance of this pie-chart (Figure 3-34)? Well, from a prototyping view point at least the double-sided PCB is extremely expensive as it consumes almost 60% of our budget!
3.6 Design Specification
A list of all of the design specifications noted above is shown in Table 3-3 below. The design specifications will be used to help develop our test specification in a future part in the series.
Table 3-3: Design Specifications
I am sure that there are many more design specifications that we can add to these ones but I will leave that as an exercise for the reader.
In this part of the series we have developed the requirement specification and have used it to analyse and select components. During this process we have also developed a design specification which we will use later on, in the series, to develop a test specification.
In part IV of the series a backlight circuit will be developed and in part V a prototype PCB design will be presented. Familiar PCB design software will be used to produce the relevant PCB manufacturing data for the prototype board to be sent to a PCB design house. So after all this is the design phase finished? Well, not really as there are always improvements that can be made to a design but this will do for now.