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Series 1: Part 5 - PCB Design Schematics and Artwork (LQ043T3DX02)


LQ043T3DX02 driver board - top layer

The objective of Series 1 of the Missing Lecture Notes (MLN) series is to develop A LQ043T3DX02 (Sony PSP) Display Driver Board. In the first section, of this part of the series, some preliminary design techniques that can ease the overall PCB design process are presented. The next section introduces thermal management and discusses how thermal analysis can be used to ensure that devices are used within the bounds of their operating temperatures. Some last-minute component value modifications and re-calculations are presented in the third section along with updated versions of the requirement and design specifications. Next the preliminary PCB schematics and artwork are presented. In the final section of Part 5 the topic of signal integrity is re-visited in an attempt to explain some of the side effects of transmission lines that could ruin the design.

1.5.1 Introduction

Over the initial four parts of the series we have put in a lot of hard work in trying to understand the PSP TFT-LCD module's interface. This has involved investigating the mechanical, electrical and data interfaces, in parts I and II, to such an extent that we have been able to define a requirements specification for the design of a prototype interface board.

The requirements specification, derived in part III, has allowed us to define the limits against which we can select our components. Also, they have provided us with a list of objectives that eventually our working prototype board should meet before the whole of the project, at the PCB design stage at least, can be deemed a success.

Furthermore, in part III we have analysed and chosen components based on the requirements specification. From the chosen components we have derived a preliminary design specification. However, a step backwards has been taken in part IV to design a more robust backlight circuit using a boost voltage regulator. Using a regulator should provide a large enough potential difference across the backlight LEDs in the LCD-TFT display module.

All of this hard work has brought the design to the stage where we can finally consider using a PCB design package to create the artwork of our prototype interface board.

Functional block diagram

 Figure 1:5-1: Updated Functional Diagram: The most recent additions are shown in orange and greyish-green. The backlight light circuit was initially described in part IV and completed in the modifications section while the touch screen controller is a new addition.

So in this part of the series, part V, the schematic entry portion of a PCB design package will be used to define the logical connections between the components. This will result in a schematic diagram which, once created, will be used in conjunction with the PCB layout part of the PCB design package to define the physical connections between the devices. Hence, we would have created the artwork of the prototype interface board.

It should be as straight forward as that, shouldn’t it? Well, as with have learnt from the previous four parts of the series unless a careful and methodical approach is taken what should be a straight forward and routine process can quite easily become overbearingly complicated at best and a nightmare at worse!

 3D generated model of the prototype PCB

 Figure 1:5-2: If everything goes well our PCB design should end up resembling this 3D generated model of the prototype board.

So from the preliminary parts list we are now in a position to start thinking about creating a schematic diagram of our prototype TFT-LCD module interface board. This usually takes the form of drawing logical connections between the schematic symbols of the devices, selected from the available schematic libraries in a PCB design package. It is not unusual however to “get the ball rolling” by sketching the organisational layout of a design on the back of an envelope as can be seen in Figure 1:5-3.

It is not uncommon for the design process to begin on the back of an envelope!

 Figure 1:5 3: It is not uncommon for the design process to begin on the back of an envelope! It is quite remarkable that the final design looks very similar to the original concept conceived many moons ago.

If the schematic symbols, available in the provided schematic libraries, are inadequate the design engineer can create his or her own custom schematic symbols. This normally happens when a required symbol does not already exist or if there is a desire to arrange the pinouts of a symbol in one’s own unique way.

Indeed creating custom symbols, even if they exist in the provided schematic library, is a popular approach taken by commercial organisations. Taking this approach helps organisations ensure that a standardized symbol and font size, as well as naming convention, is used for all their schematic symbols, irrespective of the source or PCB design package used.

Most design engineers have their own favourite PCB design software that they are familiar and comfortable with. The hobbyist engineer however can be limited to a choice of freely available software packages to perform their comparatively small-sized designs. An excellent package that fits in this criterion is Eagle (Light Edition) from Cadsoft ( If you are in need of a freeware PCB design package to follow this series it would be the one I would recommend amongst the many excellent others.

Another package fairly popular in universities and in industry is the package formerly known as Protel DXP and now Altium Designer. Ever since Protel 99 appeared on the market it has certainly left a favourable impression amongst design engineers and in my opinion it keeps on getting better. However, as mentioned previously each engineer as his or her own favourite package they swear by for varying reasons. Irrespective of the package used it is usually the quality of the design that makes the difference!

Some PCB board manufacturers also offer their own PCB packages, free of charge, that are closely aligned to their manufacturing processes. Disappointingly though, PCB design packages are still “thin on the ground” for LINUX users although good working designs can be created using the package called PCB ( No matter which package is used it always pays to plan your work in advance. So without much ado let’s begin!

1.5.2 Preliminary Design Work

It would be nice to dive in straight away and immediately start designing the schematic sheets. However, it is normally profitable to do some preliminary work up front including investigating the potential size of the prototype PCB. As discovered in part III almost 60% of our preliminary material’s budget will be consumed by the cost of the proposed 100mm x 80mm double-sided PCB. Hence, getting the artwork right the first-time around not only does one’s self-esteem “a world of good” it saves money too!

In general, the more PCB layers you use for the same sized PCB, the more expensive the bare PCB will cost to manufacture. However, the individual cost of a single PCB reduces proportionately when quantities of boards are manufactured in a single batch, compared to when the odd 1 or 2 are manufactured in isolation. Now, since the bare prototype PCB commands such a huge slice of our overall prototype budget it is worth spending some time investigating device placement and power dissipation beforehand.

Considering the junction temperature of devices and the air flow over them is generally overlooked in the majority of hobbyist digital design projects. This is usually because they tend not to be housed in an enclosure. Instead, as is the case with the prototype driver board, hobbyist projects tend to remain on the desktop and are typically operated at room temperatures. However, considering thermal analysis in every design is a good practise to maintain.

A list, Table 1:5-1 for example, can be constructed detailing the approximate area covered by each component. The maximum dimensions, of each component, can usually be found in the packaging section of the datasheet. Also, in this table, is a compiled check list of existing symbols and footprints from the available libraries within the PCB design package.

The table provides a coordinated view of the extra amount of work that should be allocated in creating the schematic symbols and component footprints missing from the PCB design package. The timescale column in the table is used to indicate the relative length of time, or man hours, needed to design the missing schematic symbols and component footprints.


Table 1:5-1: A list of major component dimensions schematic symbol name and footprint name.

Table 1-5-1: A list of major component dimensions schematic symbol name and footprint name. Mechanical Interface Considerations

Hence, we have a preliminary component list and a proposed 2-layer PCB with dimensions of 100mm x 80mm. Next, we could create a board of this size, in our preferred PCB design package, to get a feel for the board’s physical dimensions. Once this has been done and if the PCB design package allows saving or exporting the board in alternative file formats, the design could be exported as an AutoCAD exchange format file, .DXF, for use in a drawing or mechanical design package.

The newly created exchange format file of the PCB could then be imported into AutoCAD or any other type of mechanical design package or even a 3D package like Blender ( The list of component dimensions, from Table 1-5-1, could then be used to construct replica components for use on the exported PCB design, in the mechanical package, to determine the relative positioning of the devices on the board.

It could also help in determining whether the PCB will be large enough to accommodate all of the components. It may even be discovered at this stage that the estimated size of PCB is too large. As the PCB tends to be an expensive material cost, at the prototyping stage, the smaller we can make it the cheaper it will cost to manufacture. So we might need to repeat the exercise a number of times to determine the optimum dimensions of our PCB to the nearest couple of millimetres.


Prototype PCB drawing

 Figure 1:5-4 : In mixed design environments providing a preliminary layout in a mechanical design package format can be extremely useful to engineers from multiple disciplines.

The preliminary result of laying out the components on a target PCB, which measures 100mm by 80mm, is shown in Figure 1:5-4. Exporting the design as an AutoCAD file rather than saving it in an image file format, like JPEG or PNG, is extremely advantageous as packages like AutoCAD retain the board layer information as can be seen in Figure 1:5-5.

Figure 1:5-5: The PCB layer information and dimensions are preserved when a PCB design file is exported as data exchange file (.dxf) into packages like AutoCAD. The mechanical layer, also known as the comment layer, can be modified to provide extra information that can be used when the design is imported back into the PCB design package.

Thus, if the placement areas and other items, like comments, are drawn on a comment layer this information will be mechanically accurate should the AutoCAD file be imported back into the PCB design package. (For example, component positions outlined on the mechanical layer will appear on a numbered mechanical layer).

Having this detailed information, on a mechanical layer, helps in verifying the relative spacing of some of the more delicate component footprints. This is due to the increased precision and ease of use of mechanical design packages in general compared to the more basic, grid-like only, arrangements of PCB layout packages. 

Also, having the ability to export a design is also a great aid in multi-disciplinary environments where other more demanding positional considerations are made. The AutoCAD version of the PCB could be made available to mechanical or structural design engineers for stress or vibration analysis to name a few uses. Other types of analysis, including air flow and heat dissipation, can also be performed to help pre-determine relative component positions. 

It is not uncommon for a designer to pay careful consideration to the placement of voltage regulators and other devices that need a decent conduction or convection path to dissipate heat from the external casing of a device. Such devices are usually positioned to take advantage of mechanical vents or other areas of favourable air-flow determined not by the electronic design engineer but by his mechanical counterpart. 

It is unsurprising therefore that the electronic design engineer sometimes finds himself engaging in some rather heated exchanges with engineers from other disciplines about the efficacy of each discipline’s viewpoint when the placement of components takes on a multi-disciplinary approach. In fact it is not uncommon for the electronic design engineer to suggest that it is the mechanical engineers that are generating the hot-air and not the PCB! 

The technique of exporting the design, into a mechanical design package, can also be used quite effectively in mixed signal designs. This is done to investigate preliminary analog and digital design area partitioning, of a PCB, in a mixed signal power plane designs. Indeed, as a package like AutoCAD supports the LISP programming language it offers endless possibilities of writing plug-ins for heat-flow, transmission line as well as other types of analysis useful to the design engineer. Pro Engineer is another popular design package used by enclosure designers for this exact purpose.

1.5.3 Thermal Management - Characteristics, Considerations and Analysis

In more demanding designs the design engineer may also be required to pre-empt the potential troublesome temperature hotspots on a PCB, given the approximate power dissipation of each device. This requires an understanding of thermal management and how it can be used, in combination with each device’s thermal characteristics, to minimize the thermal resistance and maximize the heat dissipation.

Most component datasheets will provide data for the junction-to-case and junction-to-ambient thermal resistance of the device. The maximum junction temperature and the maximum operating ambient temperature are also provided as can be seen in the example thermal characteristics of the NCP1117 voltage regulator shown in Figure 1:5-6.

the maximum ratings of the NCP1117 voltage regulator.

 Figure 1:5-6: The maximum ratings section of a datasheet usually contains the parameters useful in performing thermal analysis as can be seen in the example above taken from the NCP1117 Voltage Regulator’s datasheet.

When two objects are at different temperatures thermal energy, otherwise known as heat, flows from the body with the higher temperature to the one with the lower temperature. This heat transfer occurs when the kinetic and potential energies of the random motion particles, within the body, are redistributed. Thermal energy can be transferred through conduction, convection or radiation.

However, when two objects are brought together there will be a resistance to the thermal energy exchange between them. This resistance is known as the thermal resistance. It is a measure of the efficiency of heat transfer from one body to another across the boundary separating the two bodies.

 Figure 1:5-7: Different Flavours of Heat Dissipation Aids. A heat sink removes heat by conduction while a fan removes heat by convection.

The thermal resistance of a component is usually quoted in the maximum ratings section, see Figure 1:5-6, as the junction-to-ambient or junction-to-case thermal resistance, (1), where ‘junction’ refers to the junction of the die enclosed within the device’s packaging. The junction-to-case value is used in calculations where a third party body is placed between the device’s case and the ambient air, a heat sink or thermal compound, for example.

In the scope of this project all thermal management calculations will use the junction-to-ambient thermal resistance value. Since, as has been stated previously, we anticipate using our prototype driver board in a modest environment without the need for any cooling aids.

Typically, the aim of thermal analysis is to determine whether a device is being operated within its allowable die junction temperature limits, (2) in Figure 1:5-6. The allowable limits are determined in conjunction with the ambient temperature of the environment and the approximate amount of heat that a device will dissipate.

The ambient temperature of the environment should never exceed the maximum operating ambient temperature of the device. Hence, as devices are operated in different thermal environments, the same device exists in multiple operable temperature ranges. The temperature ranges are classified as the military, extended (automotive), industrial and commercial temperature ranges listed in Table 1:5-2. Project prototypes normally use devices operable in the commercial temperature range.

The price of a device can vary from tens of pence to a few pounds, for a commercial grade device, to hundreds of pounds to thousands of pounds for a military grade one. For example, the price differential between commercial FPGAs and their military grade equivalents, used in satellite and space science applications, can be quite staggering. It is not unusual therefore for the functionality of a FPGA, used in such applications, to be prototyped in commercial grade devices first.

Table 1:5-2: Device Temperature Ranges
Class Lower Limit (oC) Upper Limit (oC)


-55 125


-40 125


-40 85
0 70

 The equations used to determine the maximum power dissipation are shown in Figure 1:5-8. One of the goals of performing thermal analysis, on a device, is to ensure that it is operated within its legal operating limits. Hence, by attempting to lower a device's junction temperature and consequently reducing the thermal resistance to a minimum, the amount of heat conducted from the case to the ambient air is increased.

Power dissipation equations

 Figure 1:5-8: Power Dissipation: Junction-to-ambient or Junction-to-case thermal resistance and other values are used in conjunction with a device's expected power dissipation to determine its junction temperature.

 Heat transferral, away from a device, can be done in a variety of ways including using materials that have a high conductivity. Metals used in the construction of heat sinks are useful for this purpose. Removing a reasonable volume of heat away from the device per unit time, as is the case when a fan is used, works well too. However, when using a fan there is always extra motivation in operating it outside of frequencies audible by humans. This is to minimise the annoying humming sound associated with fan cooled devices.

Another way that the thermal resistance can be reduced is by exploiting the packaging of the device as can be seen in Figure 1:5-9. In this diagram the NCP1117 and the LM317 voltage regulators are presented in the DPAK and SOP-8 pack respectively.

The thermal resistance of these devices can be reduced and as a consequence the power dissipation capabilities of the device can be improved upon by increasing the size of the copper area in direct contact with the device. Hence, the heat is dissipated through the PCB although it is always questionable where the heat goes from there.

Case thermal resistance and maximum power dissipation

 Figure 1:5-9: Case Thermal Resistance and Maximum Power Dissipation Vs PCB Copper Length.

The results of any thermal analysis can be presented in a tabulated form, as shown in the example in Table 1:5-3. At an ambient temperature of 25 degrees Celsius it is anticipated that all of the devices, used on the prototype driver board, will operate comfortably within their maximum operating temperature limits.


Table 1:5-3: Example Thermal Analysis Table

Example thermal analysis table

 This design has no requirement for a heat sink or fan so the full mantra of equations needed to determine the surface area and shape of a heat sink cannot be demonstrated here. Perhaps in a future part our driver board will be placed in a display enclosure. 

 LM317 Dropout voltage

 Figure 1:5-10: LM317 Dropout voltage Vs Junction Temperature. Taken from the LM317 datasheet.

It is not always as straight forward as one would like to determine the power consumption of a device. For some devices the best way to approximate their power dissipation might be to do so empirically using the available graphs and figures in the datasheets as in the example heat dissipation curve of Figure 1:5-10.

1.5.4 Alterations, Modifications and Finalising Calculations

 This section summarises the finishing touches applied to the design. It also tidies up parts of the design that might not have worked as expected. It has been discovered for example that applying current regulation to the backlight circuit provides an overall better design. I would like to thank Igor for his comment, yet again, in pointing out this omission. Updating the Requirements Specification

Any alterations or extensions made to the design should mean that the design specification and the requirements specification are updated accordingly. Modifying the requirements specification is the dreaded “requirements creep” that both hardware and software engineers always complain about. However, it is very rare to work in an environment where the requirement specification is cast in stone, especially given the financial and commercial pressures associated with the larger projects.

Due to the cost of manufacturing a PCB it is worth while making any modifications and additions. This is preferably to going through the process of “re-spinning” the PCB at a later date when the modifications are need and the additions are required. An updated functional diagram is shown in Figure 1:5-1 above and the associated requirements specifications are listed in the Table 1:5-4.

 Table 1:5-4: Updated requirements specification

updated requirements specification Touch Screen

 The Spartan 3A starter kit offers the user the ability to create an embedded design with a Human Machine Interface (HMI) through a PS/2 connector, as can be seen in Figure 1:5-11. However, it is becoming increasingly common for third party vendors to produce touch panels that are compatible in size to the popular LCD-TFT screens and the PSP TFT-LCD replacement display is no exception.

Figure 1-5-11: Users can interact with images and data on the PSP TFT-LCD module’s screen using a PS/2 mouse or PS/2 keyboard peripherals however if we really want to be relevant in the 21st century we can use a touch screen.

Figure 1:5-11: Users can interact with images and data on the PSP TFT-LCD module’s screen using a PS/2 mouse or PS/2 keyboard peripherals however if we really want to be relevant in the 21st century we can use a touch screen.

 A review of the current number of I/O pins, used to interface the PSP TFT-LCD module to the Spartan 3A starter kit, has revealed that the remaining unused I/O pins can be used to interface a touch panel controller to the starter kit. Hence, the combination of prototype driver board and Spartan 3A starter kit can provide human-machine interaction through the use of a mouse, a keyboard or a touch screen panel.

A touch screen panel that seems suitable for this application is the one from Sparkfun (, see Figure 1-5-11, which is produced by Han Touch USA – Touch Screen Specialists (Hantouch part # : HT043A-NCOFD52). A datasheet for the part is available from the Sparkfun website. Touch Screen Connector

The touch screen panel users a standard FFC/FPC 1mm pitch, 4-pin connector available from most connector vendors like the one shown in Figure 1:5-12 from FCI Connect (Part #: SFW4R-1STE1LF).

Touch screen panel flexible cable

 Figure 1:5-12: Touch screen panel flexible cable and compatible connector. (All measurements are in mm.) Touch Screen Controller

Touch screen controllers are available from Texas Instruments and Analog Devices and probably other major component vendors as well. The ADS7843E device has been chosen randomly based on the experiences of other users, of the device, on the Internet and because of its undemanding interfacing requirements.

ADS7843E Touch screen controller

 Figure 1:5-13: ADS7843E Touch Screen Controller Device.


The main characteristics of the device are its 125 KHz conversion rate and its use of an ADC that has a programmable resolution of 8 or 12-bits. This device will be reviewed fully in a future part of the series when device drivers, to control and read data from it, have been written.

A characteristic that we should pay attention to now however are the input and output voltages characteristics. Figure 1:5-14 shows that these are fully compatible with the Spartan 3A FPGA when the FPGA’s I/O pins are configured at 3.3V LVTTL levels [DS12]. Any unused inputs on the ADS7843E should be tied to ground [DS13].

Figure 1-5-14: The voltage levels of the ADS7843E are compatible with the LVTTL I/O levels of the Spartan 3A starter kit. 

 Figure 1:5-14: The voltage levels of the ADS7843E are compatible with the LVTTL I/O levels of the Spartan 3A starter kit.

Finally, we should remember to decouple the ADS7843E input and reference voltages [DS14]. Regulating the Backlight Circuit Current

As noted, in a previous part of the series, the backlight of the TFT-LCD panel consists of 7 white LED’s in series each with a forward voltage, VF of between 2.5V and 3.2V. The LEDs are commonly placed in series so that the same amount of current flows through each one. This helps to maintain a constant luminosity across all seven LEDs.

If we approximate the forward voltage to 3.0V then at least 7 x 3.0V or 21V must be applied across the LED’s before they will begin to conduct current. In the last part of the series a boost regulator circuit has been developed to create a high output voltage from a smaller input voltage for this very purpose.

It is also required however that the current is regulated to avoid fluctuations in the voltage supply from momentarily affecting the brightness of the display. To regulate the current the LM317L which is a 100ma adjustable output, positive voltage regulator is used in a current regulator configuration as can be seen in Figure 1:5-15.

Figure 5 15: The MC34063A boost regulator circuit and the LM317L voltage regulator used as a current regulator supply the power requirements to the seven backlight white LED’s.

 Figure 1:5-15: The MC34063A boost regulator circuit and the LM317L voltage regulator used as a current regulator supply the power requirements to the seven backlight white LED’s.


To achieve this circuit the output voltage of the MC34063A should be modified to output roughly 35V to accommodate the voltage drop across the LM317L regulator and across the series resistors R1 and R2. The value of the resistor, R1, is determined by setting the maximum output current, Iout, to 20ma (a value defined in the TFT-LCD modules datasheet). The current is determined by using equation (1) while the potentiometer, R2, is used to control the brightness of the screen by limiting the value of the output current by using equation (2) in Figure 1:5-15.

Figure 1-5-16 : LM317L Electrical Characteristics

 Figure 1:5-16 : LM317L Electrical Characteristics

In the last part of the series the component values of the MC34063A configuration have been determined manually by using the equations provided in the datasheet. Rather than determining the values manually, each time a new configuration is needed, an Octave ( function has been written to determine the MC34063A passive component values. The output from the Octave script can be seen in Figure 1:5-17.

Figure 1-5-17 : Output from the Octave function used to determine the MC34063A passive component values.

 Figure 1:5-17 : Output from the Octave function used to determine the MC34063A passive component values.


Additional design specifications that could be derived from the backlight circuit include the following: The minimum voltage into the backlight circuit should be 4.5V [DS15]. The maximum output voltage of the MC34063A circuit should be 35V [DS16]. The maximum current available to the backlight LEDs should be 20ma [DS17].

Figure 1-5-18 : Simulation results of the output of the MC34063A voltage regulator in a boost configuration.

 Figure 5-18 : Simulation results of the output of the MC34063A voltage regulator in a boost configuration. The Potentiometer

As described previously a potentiometer is used to provide brightness control by reducing the amount of current available to the backlight LED’s. Choosing a potentiometer can be quite tricky given the amount of choice from online, electronic catalogue vendors.

The 1K potentiometer shown in Figure 1:5-19 has been chosen due to its small form factor although any potentiometer should probably do. A possible disadvantage of this device though is the requirement of having a screwdriver or similar device nearby to adjust it. Maybe a device with a knob might have been better!


 Figure 1:5-19: Potentiometer used to control the PSP TFT-LCD modules brightness. The Bulk Capacitance

 In the end a bulk capacitor with a value of 330uF (16V) has been chosen from experience and observation more than anything else. Given more man-hours to work on this part of the project it would have been good to go through the permissible input ripple voltages of each device. This would have allowed us to work out the minimum amount of bulk capacitance needed when the input voltage drops by 10%, for example. However, 330uF will suffice for now. Additional Design Specifications

 Any design specifications resulting, from modifications and additions, should also be added to the design specification list, Table 1:5-5. As mentioned previously this is not an exhaustive list of design specifications but enough to help in the exercise of designing a test specification which will be covered in a future part of the series.

  Table 1:5-5 : Updated Design Specifications


1.5.5 PCB Design Component Schematic Symbols

As mentioned previously a schematic symbol is usually created if it does not already exist in the huge built-in libraries, or if a custom symbol is required for aesthetic, or other, reasons. Most electronic project hobbyists do not have the rich compliment of output devices such as the A3, A2 and A0 printers and plotters readily available to commercial organisations. It is important therefore to make the pin spacing on schematic sheets a reasonable distance apart, such that they are readable on the printout of the typical A4 printer used by the hobbyist. An example of this can be seen in Figure 1:5-20.

 Then schematic symbols are created assigning the correct pin properties of Input, I/O, Output, Open Collector, Passive, Hiz, Emitter and Power can help when an Electrical Rule Check (ERC) is performed. Although this is not always done on the completed schematics of small designs as it is not “always” critical. However, using all tools available offers the designer more chance of achieving success first time around.

Figure 1-5-20: Example construction of the ADM6820 schematic symbol from its datasheet.

 Figure 1:5-20: Example construction of the ADM6820 schematic symbol from its datasheet. PCB Footprints

 Oncethe schematic symbol has been completed it is not uncommon to allocate a footprint immediately afterwards from the existing footprint libraries. Most datasheets provide a package description against which the footprint can be searched. Extreme care must be taken when choosing footprints as names can be deceptively similar. Hence, it always helps to choose a footprint from the same manufacturer if possible.

Figure 1-5-21: Example PCB Layout Footprint

 Figure 1:5-21: Example PCB Layout Footprint.

However, if a custom footprint must be created it is sometimes useful to draw the footprint on paper first, before designing the footprint in the PCB package. This helps clarify any uncertainty with dimensions and could prevent designing a footprint in inches from the millimetre dimensions as a student I know once contrived to do! Needless to say the student was extremely surprised the device did not fit the footprint once the PCB had been manufactured. Netlist Naming Conventions 

Providing schematic signal nets with meaningful names, in relation to the components that they connect to, aids in the readability of the schematic. There are countless netlist naming conventions including using an abbreviation of the device name as a prefix for the netlist signal name.

For example, all of the signals associated with the TFT-LCD module’s interface might be prefixed with a TFT_. Then instead of the names of the netlist connected to the TFT-LCD module having partly meaningful and sometimes ambiguous names like HSYNC, VSYNC, R0, R1, etc they become instantly recognisable with names like TFT_HSYNC, TFT_VSYNC, TFT_R0 and TFT_R1.

A schematic sheet should be designed such that it can be quickly read when things go wrong and 99% of the time they will. When things do go wrong the more legible the design is the easier it will be to debug. Remember that it is not uncommon to revisit a schematic many months after its initial design and if the components are laid out in a logical manner, that follows the flow of data in the design, the easier it will be to read.

The time between when a schematic is created and the board is laid out, devices and connectors are ordered, the board is manufactured, test code is written and the board finally assembled, tested and debugged could be very long indeed. It is not uncommon therefore to have completely forgotten about the finer stabilising details that have been added to tweak (one could argue fudge!) the design to improve its performance. Hence, comments should be liberally used on the schematic. A useful technique to consider is to allocate one major component per schematic sheet or at least keep similar functionality on the same sheet.


1.5.6 PCB Design Mechanical Considerations 

 Initially, in the design of a prototype driver board the idea was to design a board with dimensions of about 100mm x 80mm or smaller in size as discussed in section 1 above. However, partly for aesthetic reasons a prototype board that measures 120mm x 70mm has been designed as can be seen in Figure 1:5-22. This length of prototype board has also been chosen so as not to obscure the two 6-pin Digilent connectors seen in the same Figure.

 Figure 1:5-22: The final dimensions of the prototype TFT-LCD module driver board ended up being 120mm x 70mm for aesthetic reasons more than anything else. 

When considering the mechanical dimensions of the PCB it is also worthwhile considering how it will be mounted. M3 mounting holes are typically placed at the four corners of a board. For this particular project however as the Spartan 3A starter kit uses mounting pads instead of spacers it has been decided not to provide mounting points on the prototype driver board.

 Figure 1:5-23 : Dimensional relationship between the backlight, power and data and touch screen panel connectors.


The relationship between the connectors should also be considered careful too. Figure 1:5-23 shows the relative positioning of the backlight, the power and data connector, and the touch screen connector. The figure shows how they have helped influence the shape and size of the prototype PCB. Planning the Board Layers  

Figure 1:5-24 : The PCB stack of the TFT-LCD Module Drive Board.

 Figure 1:5-24 : The PCB stack of the TFT-LCD Module Drive Board.

When planning board layers the use of power planes should be thought of careful, as well as the edge rates of the data signals. Many multi-layer boards dedicate whole layers to a single signal type. For example, LVDS TX signals could be placed on one layer and the LVDS RX signals could be placed on a different layer.

The biggest influencing factor in the number of layers used on the TFT-LCD module driver prototype board has been the PCB manufacturing cost. As only two layers are used, see Figure 1:5-24, extra attention should be paid to signals with fast edge rates. A detailed discussion is provided in the transmission lines section below.

Generally, when designing two layer boards aim to place components and signal traces on the top layer and reserve the bottom layer for a continuous distributed ground plane, where possible.


1.5.7 Updated Bill of Materials (BOM)


 Table 1:5-6: The Bill Of Materials (BOM)

  Table 1:5-6 Bill Of Materials


1.5.8 Putting it All Together Schematic sheets

The schematic sheets of the PSP TFT-LCD Module Prototype Driver Board are presented below. Generally, right clicking on an image and selecting "View Image" produces a larger and clearer image, in Firefox. Alternatively, in Google's Chrome right-click on an image and select "Open image in new tab".


Figure 1:5-25: Voltage Regulator and Power Sequencer Circuit.

Figure 1:5-25: Voltage Regulator and Power Sequencer Circuit.

 27MHz oscillator and Serial FLASH Memory

Figure 1:5-26: 27MHz Oscillator and Serial SPI Flash Memory.

Figure 1:5-27: MC34063A and LM317L Voltage Regulators used to drive the Backlight Circuit. 

(Update 30/05/09 VLED- should be on pin 1 and VLED+ should be on pin 4 - B.P) 

Figure 1:5-28: Spartan 3A FX2 Connector Interface. (Resistor R15 should be a pull-down resistor - B.P).

Figure 1:5-29 : TFT-LCD Module Interface.

Figure 1:5-30 : Touch Screen Panel Interface Circuit: The schematic symbol of the ADS7843E is provided in the built in library. Notice the obscured clarity compared to the other symbols that have been specifically created for the project.

Figure 1:5-30 : Touch Screen Panel Interface Circuit: The schematic symbol of the ADS7843E is provided in the built in library. Notice the obscured clarity compared to the other symbols that have been specifically created for the project. (The ADM_nCS signal could be pulled down with a 10K resistor - B.P)

5.8.2 PCB Artwork

Figure 1:5-31: LQ043T3DX02 Driver Board - Prototype Top Layer.

Figure 1:5-31: LQ043T3DX02 Driver Board - Prototype Top Layer.


Figure 1:5-32 : LQ043T3DX02 Driver Board – Prototype. Diagram shows the routing of the top layer (red) and bottom layer (blue) signals. The High speed signals have been routed uninterrupted between the TFT-LCD module connector and the FX2 connector.


Figure 1:5-33 : LQ043T3DX02 Driver Board – Prototype. Even though a two-layer PCB has been used, with careful routing of the signals it is still possible to construct a decent distributed ground plane as can be seen in the diagram. The green squares with the hole in the middle are the positions of the test points.


1.5.9 Fast Edge Rates, High Frequency Signals and Signal Integrity

 In this section a discussion is presented on the use of controlled impedance lines and how, by adhering to known design rules, the design nightmares and disappointments associated with signal integrity can be avoided. Microstrip Transmission Lines

In the previous part of the series a star topology layout technique has been demonstrated to help avoid signal contamination. This technique works really well for low frequency signals that are transmitted, from a source to a load, as an instantaneous changing signal.

However, at high frequencies we need to take a different approach as signals are transmitted more like the travelling waves we are more accustomed to hear physicists talk about. This means that PCB layout techniques for low frequency and high frequency signals should be treated differently.

One of the main reasons why low and high frequency signals should be treated differently is because of their return currents. While the return currents of low frequency signals prefer to take the path of least resistance, the return current of a high frequency signal tends to travel along the path of least impedance.

This is because a transmitted signal and its return current form a current loop. The larger this current loop is, the greater is the loop inductance, as inductance is proportional to the area of a current loop.

Now, since the impedance, Z = 2(pi)fL, is proportional to the frequency and inductance, signals will have their return current path impeded as the signal frequency increases. At very high frequencies the effect of the impedance on the signal can no longer be ignored. In the star ground configuration, used in low-frequency designs, the trace inductance becomes so large that the configuration is no longer useful in high-frequency designs.

 Thus, while it is okay to layout return path signal traces in a star like topology for low frequency signals, for high frequency signals we should strive to reduce the inductance of the return signal path to a minimum. One way to do this is to present a distributed or solid ground plane to the return current as opposed to using individual signal traces.

Using a distributed ground plane also helps because the return current of high frequency signals strive for their path to run directly underneath the high frequency signal. By using a solid ground plane and limiting the use of vias, along the return signal path, the return signal current can take its preferred route. Also, a solid ground plane helps to reduce the associated radiation generated from the current carrying loop as the loop formed by the signal and its return current is minimized.

So what classifies a design as being in the low or high frequency domain? Well, to fully answer this question we need to understand the transmission line technique of transferring energy from one place to another in general. In particular, we need to understand how the PCB microstrip transmission lines, used on the prototype driver board, transfers information at high frequencies from the FPGA driver board to the TFT-LCD module.

The main reason why microstrip transmission lines are used on our prototype driver board, instead of stripeline transmissions lines, is to minimise the manufacturing cost of the PCB. If we are prepared to pay for the extra expense of fabricating a four or more layer board, then stripeline transmission lines would have been just as suitable, if not better.

 However, as shown in Figures 1:5-32 and 1:5-33 above with careful routing it is possible to offer a distributed ground plane in two-layer PCB designs. The rest of the discussion in this section will deal with microstrip transmission lines, although the same principle applies to stripeline transmission lines.

Figure 1:5-34: Microstrip transmission line characteristic impedance equation (approximation).

Transmission line energy transfer occurs when high frequency signals transfer their energy, from one point to another, by propagating waves with a velocity, VP. This wave propagation arises due to the conducting medium presenting itself to the source as an infinite number of inductor and capacitor pairs. 

Transmission line energy transfer occurs when high frequency signals transfer their energy, from one point to another, by propagating waves with a velocity, VP. This wave propagation arises due to the conducting medium presenting itself to the source as an infinite number of inductor and capacitor pairs.

 These inductor and capacitor, or LC pairs, dominate the transmission type at high frequencies. At low frequencies however the LC pair effect is negligible and the transporting medium reduces to an ideal wire.

So what happens exactly? Well, if we refer to Figure 1:5-35 then before a signal’s energy is transferred, from a source to a load, the energy is firstly transferred to the magnetic field of the inductors and the electric field of the capacitors. This happens whenever the source signal value changes. Associated with this energy transfer is a charge and discharge time that creates an infinitesimal delay for each LC pair.

This energy transferral occurs in turn for each pair, from source to load, as the signal propagates down the medium and finally reaches the load after a total time delay, Td, which is dependent on the length of the cable. Hence a crucial parameter in high frequency designs is the length of the transmission line.


Figure 1:5‑35 : Reflected and Transmitted Waves along Transmission Line

Now when an electromagnetic wave crosses a boundary of differing impedances, for example between the transmission line and the load and between the transmission line and the source, part of the wave is transmitted and a fraction of it is reflected. The transmitted portion of the wave is absorbed by the load, while the reflected part of the original wave heads back towards the source. When the reflected wave reaches the source it encounters another change of impedance due to the boundary between the transporting medium and the source. Hence an even smaller fraction of the reflected wave is retransmitted back to the load.

The end result is a number of transmitted and reflected waves of varying magnitudes moving from left to right and right to left decaying in time as they are absorbed and reflected by the source and load. As these waves originate from the same source they are coherent and hence interfere constructively and destructively as they reach the load at different times. The main effect of this interference on the received signal levels, at the load end of the transmission line, is ringing and the consequence of ringing is signal contamination. The signal received at the load will not be at the expected logic level.


 Figure 1:5-36 : Inappropriate signal routing can lead to transmission line side effects.

The transmission line on a two-layer board is described as a microstrip line when the top layer signal trace is referenced to a distributed ground plane. The propagating signal or wave, along the trace, is partly embedded in the board and partly in air. The type of transmission line model to use to characterise a PCB trace is important. By knowing the type of transmission line the impedance of the trace can be controlled.

We can control the characteristic impedance of the line by adjusting the height above the reference plane, the width of the line (signal trace) or even, in extreme cases, by altering the dielectric medium the travelling wave propagates through. By controlling the characteristic impedance of the line we can minimise the amplitude of the reflected waves. This is done by attempting to match the characteristic impedance of the transmission line, seen by the source, to the load impedance. This has the overall effect of eliminating ringing and other transmission line side effects at the load.

Unfortunately, when we step out of the analytical world and into the real world limits in PCB manufacturing technology means that constructing a transmission line with ideal characteristic impedance is not always possible. For example, the height of the signal trace above the reference plane is limited by PCB layer stacking technology.

Advances in laser etching technology however has meant that the PCB traces can now be made narrower and placed closer together than ever before. This has resulted in the design of transmission lines with characteristic impedances vary close to analytically calculated values.

So, in effect, by adjusting the characteristic impedance of a transmission line the general aim is to reduce the amplitude of reflected waves. The reduction, in amplitude, of the reflected waves, reduces transmission line side effects at the load. Quite interestingly however most of us have designed PCBs, with high frequency signals, without worrying about transmission line effects and the designs have worked reasonably, if not perfectly, well. There is a logical explanation why which is presented next.

Let’s revisit our 27MHz oscillator introduced in part 2 of the series. The oscillator produces a clock signal that has rise and fall times of 5ns. As a single clock pulse, it is transmitted from source to load as a propagating wave on a transmission line. The wave has a propagation velocity of

 Vp = C / sqrt(Er) where C is the velocity of light (in free air) and Er is the electrical permittivity constant of the medium.

 For an FR4 material the permittivity constant is generally regarded to be between 4.0 and 5.0 depending on the transmission line type and the material’s tolerance. For a microstrip line as the waves partially travel through air and partially through the FR4 material determining the effective relative permittivity constant is not straight forward. However, let’s say that the effective relative permittivity constant is approximately 4.5 and that the speed of light is approximately 2.99 x 108 m/s in free air. The velocity of propagation of our clock signal is determined as

 Vp = C/ sqrt(Er) = 2.99 x 108 / sqrt(4.5) = 1.41 x 108 m/s.

 And knowing that distance = velocity x time where time = 1/3 x (signal) rise time, then we can determine the critical length, L, of the trace or the length of the signal trace where signal integrity effects will be noticed as


L = time x Vp = 1/3 x 5 x 10-9 x 1.41 x 108 = 2.35 x 10-1 m = 0.235m

or 23.5 cm. Since, most hobbyists’ prototype boards are typically small (less than 160 mm by 100 mm) they will not be affected with signal integrity problems.  This is especially so when a clock signal, with an edge rate of 5ns, is used and the signal trace is sensibly routed. Hence, on our prototype driver board as long as our clock’s signal trace is less than the critical length we should not witness any SI problems, assuming other SI rules have not been violated of course.  

Now, supposing we see an alternative oscillator, similar to the one chosen for this project, but more expensive because its output better resembles a square wave. That is, its output signal has rise and fall times of 0.5ns. We could decide to buy this alternative oscillator as a drop-in replacement. Now supposing our clock signal trace is 5cm long. If we recalculate the critical length, L, then


 L = time x Vp = 0.5/3 x 10-9 x 1.41 x 108 = 0.47 x 10-1 m 0.047m = 4.70 cm.

 All of a sudden what was a perfectly working design stops working at best or worst of all works intermittently because our routed trace of approximately 5cm is now longer than the critical length 4.70cm.

So if you have not had problems up to now you can see why. As long as the rise time of a signal is longer than the transmission line delay and hence the critical length of the transmission line, reflections should not occur.  This is due to the reflections decay between the clock signal pulses. On the other hand, if the rise time is shorter than the transmission line delay then overshoot and ringing could be noticed.

We are now in a position to answer the question of what constitutes a high or low frequency signal design. If the rise times of signals in the design are short compared to the transmission line delay, Td, then the design is considered to be in the high frequency domain. When the rise times of signals are long, compared to the line delay, Td , then signal integrity effects go unnoticed and the design can be considered to be in the low to medium frequency domain.

For most applications, a general rule of thumb is that if the rise time is greater than 6 times the transmission line delay then the design is considered to be a low frequency one. Conversely, if the rise time is shorter than 6 times the transmission time delay then the design can be considered to be a high frequency one.

Specialist software applications (e.g. Mentor’s Hyperlinx) are available for transmission line analysis. Such software, typically, incorporates specialist 2D and 3D field equation solvers. However, they are extremely expensive to purchase. The best way to eliminate the effects is to stick to some basic rules and do some work up front to help minimize the side-effects that affect signal integrity.

As stated previously, signal integrity is a huge topic and by providing this example we have only scratched at the surface of a very immense and complicated, but important, PCB design subject. As the clock rates used in designs with FPGAs become higher and higher, transmission line effects will increasingly dominate PCB design issues. One only needs to look at the next generation of feature rich FPGAs and high speed transceivers to find out why.

A famous quote that can be used to summaries this section is: “There are two types of engineers, those that have had signal integrity problems and those that will.” There is no doubt that we will revisit the topic of Signal Integrity in a future series.


1.5.10 Conclusion

 Well, this part of the series is much longer than I anticipated it would be but it is nice to finally have a prototype PCB design that can finally be sent away for manufacture. 

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