- Created on Sunday, 07 August 2011 05:36
- Last Updated on Tuesday, 16 July 2013 06:13
Altera's Cyclone III FPGA Starter Kit contains an entry level Field Programmable Gate Array (FPGA) development board concentric about a Cyclone III FPGA. Although it could now be considered archaic, given that Altera have enhanced the Cyclone family of FPGAs with Cyclone IV and Cyclone V devices, it is still useful as a hardware development tool. Its credentials as a useful hardware prototyping platform are justified given that it has most of the major hardware components encountered in entry-level hardware development.
This article reviews the architecture of the FPGA development board, contained in the starter kit, and investigates how it can be expanded into a robust hardware development system.
The layout of the development board included in the Cyclone III Starter Kit can be seen in the annotated diagram of Figure 1 below. The kit is supplied with a more than adequate set of documentation, including board design files and tutorials, to get the user started.
The primary components on the Cyclone III starter board are:
- A Cyclone III EP3C25 FPGA in a fineline BGA 324-pin package. The EP3C25 is characterised by having 66 M9K memory blocks, 66 multipliers and 20 global clocks. It has 215 maximum I/O pins of which 84 are available to the user via an expansion header.
- An assortment of memory devices including 16MBytes parallel flash, 32-MBytes Double Data Rate (DDR) SDRAM and 1MByte SSRAM.
- User LEDs and push-button switches.
- A built-in USB Blaster and
- A High Speed Mezzanine Connector (HSMC) that allows the user to connector daughters boards with as many as 84 I/O pins.
This list of features is summarised in the block diagram of Figure 2 below.
Not all of the memory components listed above, in item 2, are available concurrently however, as the parallel flash and SSRAM share address and data buses . While this list of on-board components is impressive and given that the example tutorials utilise the USB Blaster to provided user feedback to a PC, its limited PC connectivity is disappointing. The Cyclone III starter kit is somewhat let down by the lack of any form of medium-speed serial or USB connectivity.
For this FPGA development board to be really useful what is required is a thorough understanding of the HSMC mezzanine connector and how it can be used to provide additional hardware resources to enhance those already provided. The rest of this article therefore concentrates on this external connector.
The HSMC External Interface Header
As mentioned previously the HSMC header, see Figure 3. is required to interface user defined peripherals to the Cyclone III Starter Kit, The header is a proprietary one manufactured by Samtec for Altera. The aim of supporting a standardized connector for host development boards is to allow hobbyists and commercial manufacturers alike to build a single mezzanine card that can interface to multiple host boards. Similarly, a host board can be designed to support different mezzanine cards.
According to the information obtainable on Samtec's website "... The HSMC connectors defined by the specification are based on the 0.5mm pitch Q Strip® QSH/QTH series high speed board-to-board connectors from Samtec. The host board connector is Samtec part number ASP-122953-01 (a modified QSH series). The mezzanine (daughter) card connector is Samtec part number ASP-122952-01 (a modified QTH series)".
A daughter card designed to interface to the Cyclone III starter board should be populated with the ASP-122952-01 Altera connector or the standard unmodified QTH-090-01-L-D-A connector. When a cursory glance is paid to the Cyclone III starter board's schematic sheets, included with the starter kit, it is soon noticed that all of the FPGA's I/O banks are connected to the 2.5V power rail, as can be seen in Figure 4. The consequence of this is that the voltage levels that the HSMC header's I/O pins can be configured to are limited.
Hence, care should be taken when selecting components for a daughter board. The I/O pins of the interfacing component's receiver and transmitter should be compatible with the voltage levels of the I/O pins on the HSMC header connected to the FPGA. The voltage level is likely to be either 2.5 LVTTL, 2.5 LVCMOS or 2.5V LVDS depending on the I/O standard selected when configuring the FPGA. Altera have published an extensive answer note2 on the ins and outs of interfacing the 2.5V logic of Cyclone III devices to peripherals with I/O receivers, and transmitters, with 3.3V and higher logic voltage levels.
The Altera Cyclone III Starter Kit is a versatile entry level hardware development platform consisting of a board populated with a EP3C25F Cyclone III FPGA. Although the Cyclone III is not the most recent in Altera's Cyclone family of FPGAs, it is robust enough to support hardware development for all but the most demanding of applications areas. The starter board is accompanied by a rich array of memory devices and a substantial I/O expansion interface.
The lack of a medium to high-speed communications interface could be regarded as a glaring omission however, the expansion header could be used to add many external peripherals including communication devices. Overall this is a great development kit for experimenting in hardware designs using FPGAs. The next article in the Altera notes series will investigate developing a daughter (mezzanine) card to attach to the Cyclone III starter board.
- Cyclone III FPGA Starter Board Reference Manual, v1.3, Altera Corp., July 2010.
- Interfacing Cyclone III and Cyclone IV Devices with 3.3/3.0/2.5V LVTTL/LVCMOS I/O Systems, AN447,v2.0, Altera Corp., November 2009.