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Tutorial 1: Part 6 - A Transmission Arbitration Module

0000630To alleviate the poverty of flexibility in our existing design, described in previous parts of the tutorial, a revision to the design has had to be considered. This has resulted in the development of a transmission arbitration module. Thus, the overall objectives of part six, of tutorial series 1, is to firstly design and implement a round-robin transmission slot arbitration module that can be used in conjunction with the UART module developed previously. Then, secondly, a real-world example should be demonstrated on the DE0-Nano Development Kit platform.

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Tutorial 1: Part 5 - Verifying and Testing the FSDM UART Core

1.5.1 Introduction

100038Previously, in the first installment of the tutorials, a standalone UART core has been developed, which can transmit and receive data at a fixed rate of 115,200 Baud. This rate has been considered to be general enough for the core to be useful experimentally. This indeed has been the case and the UART IP core has been demonstrated to  communicate between the USB port of a PC and a DE0-Nano Development Kit using a USB to Serial UART converter (CP2102). Before continuing development, with the implementation of the transmitter path of the protocol wrapper, we shall look at verifying and testing the UART core in this part.

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Tutorial 1: Update 20130607: FPGA Serial Debug Protocol (FSDP)

Pep Talk

100030Most scientists and engineers would agree that one of the hardest tasks in their profession is continuing on a project from where it was left a year ago or so. However, on this project, as a testament to how well the existing code has been written, nearly all the time, and not so well some of the time, we have been able to revisit this tutorial and spend very little time in trying to understand what has been done previously. Sterling documentation and an adherence to good coding standard guidelines has made restarting this project painless. A positive vote for systems engineering.

pep talk - A speech of exhortation, as to a team or staff, meant to instill enthusiasm or bolster morale - The Free Dictionary

Read more: Tutorial 1: Update 20130607: FPGA Serial Debug Protocol (FSDP)

Tutorial 1: Part 4 - Java Software Specification and Design (Part 1)

1.4.1 Introduction

0000435aThe aim of this part of the series  is to create a boilerplate FPGA Serial Communication Debug Module Application, using the Java programming language.  The NetBeans Integrated Development Environment (IDE) will be used for the application development. The application will be used to send and receive messages from a FPGA Serial Debug Module, embedded in a FPGA. 

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Tutorial 1: Part 3 - The Unified Control and Status Register

1.3.1 Introduction

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The aim of this part of tutorial series 1 is to architect and implement the control and status registers. If all goes well we should be able to connect their outputs to the inputs of the, yet to be developed, protocol wrapper TX core. Then we should be able to test the setup in real hardware, similar to the loop back test performed in part 1 of the tutorial.

Read more: Tutorial 1: Part 3 - The Unified Control and Status Register

Tutorial 1: Part 2 - The Protocol Wrapper RX Implementation

1.2.1 Introduction

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In the last part of the tutorial we managed to establish a beachhead into the design by demonstrating a UART loop-back test. Although our test procedure was rudimentary,  it allowed us to pass a very significant milestone. We were able to prove the connectivity between the PC, the UART to USB serial converter module and the DE0 Nano development kit. Also, two important aims of the project have been achieved.

Read more: Tutorial 1: Part 2 - The Protocol Wrapper RX Implementation

Tutorial 1: Part 1 - A DE0-Nano Serial Communications Protocol

1.1.1 Aim

0000392The aim of this tutorial is to use a USB-to-UART converter module to provide serial communication between a PC and user logic within the FPGA, on the DEO-Nano Development Board. Application software on the PC should allow reading from user defined status registers and writing to user defined control registers in the FPGA. Typically, the application software should communicate with the USB-to-UART bridge using virtual com port device drivers. Hence, the software should treat the USB port as a serial one. 

Read more: Tutorial 1: Part 1 - A DE0-Nano Serial Communications Protocol