- Created on Friday, 07 June 2013 20:20
- Last Updated on Monday, 24 June 2013 16:28
Most scientists and engineers would agree that one of the hardest tasks in their profession is continuing on a project from where it was left a year ago or so. However, on this project, as a testament to how well the existing code has been written, nearly all the time, and not so well some of the time, we have been able to revisit this tutorial and spend very little time in trying to understand what has been done previously. Sterling documentation and an adherence to good coding standard guidelines has made restarting this project painless. A positive vote for systems engineering.
pep talk - A speech of exhortation, as to a team or staff, meant to instill enthusiasm or bolster morale - The Free Dictionary
Its been more than a year, spring 2012, since the foundations of the DE0-Nano Serial Comms Debug Module were firmly placed on the launch pad with abated anticipation. However, that anticipation was soon dampened due to commitments to other "We need to put food in our mouths" projects. Hence, the tutorial series never really took-off.
Now, due to the urgent need of some of our own emerging projects, requiring such a module, this tutorial series will be progressed with enhancements making it more robust than before (Its being logically progressed into a leaner and meaner module - Ed).
The FPGA Serial Debug Monitor (FSDM)
This set of tutorials shall be continued as a general purpose FPGA Serial Debug Monitor (FSDM), which utilises our FPGA Serial Debug Protocol (FSDP). A top-level diagram of the monitor's revised architecture, compared to the one introduced previously in Part 1, can be seen in the Figure 1 below.
Figure 1: The revised architecture of revision 1.0 of the FPGA Serial Debug Monitor.
As can be seen, in the Figure 1, the Error Register and the Statistics Engine Register have now been assigned their own individual opcodes, which allows them to be used as addressable registers. The functionality of each unit is listed, in Table 1, below.
Table 1: A listing of the individual units within the FPGA Serial Debug Monitor and their functionality.
|UART Module||N/A||-||At the heart of the FSDM is a UART.|
|Protocol Wrapper||N/A||-||This module is used to interpret the incoming and outgoing messages.|
|Control Register||0x01||W||Can be used to control signals within the FPGA.|
|Status Register||0x03||R||Can be used to retrieve data from the FPGA.|
|User Defined Register||0x05||R/W||Allows users to define their own message layer within the FSDP.|
|Error Register||0x07||R||Used to address the internal registers e.g number of errors, etc|
|0x08||Responds to unknown and undefined message errors.|
|Statistics Engine||0x09||R||Allows the user to Retrieve data usage information.|
As introduced previously, in earlier installments of the tutorial, each register's opcode has a corresponding response code, which helps identify the source of a message received in response to a request.
The FPGA Serial Debug Protocol
The FPGA Serial Debug Protocol (FSDP) protocol is a transmit-receive one. Hence, the sender of each message received by the FSDM receives in turn either a valid response message or an error one. Messages that send packets of data to the FSDM, typical of write messages, which do not have a response are validated with an acknowledgement message.
Figure 2: Typical Read, Write and User Defined Message Formats.
As can be seen, in Figure 2, messages that read from, or write data to, the FSDM firstly send the opcode identifying the unit being addressed, followed by the number of the register within the unit being addressed. A write register message additional sends a 32-bit data word. Response packets are expected to use the same message format.
On the other hand the format of user defined messages differs slightly from the register read write ones. In user defined messages the opcode is followed by the number of bytes, N, in the message, which is followed by the message payload of N bytes. Although the protocol is expected to mature as new ideas are incorporated and old ones are discarded the format of messages, previously described, is not expected to change.
Previously, during development of the FSDM and FSDP, testing has been performed using USB to Serial converters, which have been based upon the CP2102 chip set, from Silicon Labs. The converter was connected to the DE0-Nano Development and Education Kit, reviewed previously, which hosts Altera's Cyclone IV FPGA. A typical USB to serial converter that uses the CP2102 has been reviewed previously too.
Figure 3: The 2 x 13 Way Mixed Signal Dilettante Board can support either FTDI's RS232RL Breakout Board or an Arduino RS232 Serial Shield. In this picture the Dilettante Board, which connects to the 2 x 13 way header of the DE0 Nano Development Kit, is fitted with the RS232RL Breakout Board.
Development work on the module and protocol will be continued in new parts of the tutorial uisng our new 2 x 13 Way Mixed Signal Dilettante Board (see Ben's associated Blog articles). The board, which will be described in more detail on its product page, can be seen, in Figure 3, above hosting the RS232RL Breakout Board. In addition more recent FPGA development kits, like Arrow's SocKIT Evaluation Kit hosting Altera's Cyclone IV FPGA will also be used. As this is a general purpose FPGA debug monitor other boards and kits supporting other FPGAs from other vendors will also be supported.
The series Tutorial 1, The DE0 Nano Serial Communication Debug Module, will be continued as a general purpose FPGA Serial Debug Monitor (FSDM) using the FPGA Serial Debug Protocol (FSDP). Alongside the DE0 Nano Development Kit, the monitor will be tested on other FPGA development boards and kits too, such as Microsemis's Smart Fusion 2 Starter Kit.